[SI-LIST] Re: 1000Base-T Transmitter Distortion Testing
- From: Matthew Fornero <mfornero@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 7 Aug 2012 10:42:46 -0400
Just a quick update:
I re-ran the tests using a 10 cm cable (instead of 60 cm), and now I get a
roughly 50% pass rate for the 82574. I also tested an Intel board that uses
the same chipset (EXPI9301CTBLK), and get the same results: ~90% fail rate
with 60 cm cable and ~50% fail rate with 10 cm cable. At this point it
seems that the issue is likely not related to my PCB design, but rather
with either the measurement setup or something within the IC.
My scope is a Tek DSA70604 (25 GS/s), using P7360A 6 GHz differential
probes. I'm using the TF-GBE compliance testing software and the included
jig boards (similar to the text fixtures described in the spec).
Any thoughts on this?
Best Regards,
Matthew Fornero
On Fri, Aug 3, 2012 at 11:18 AM, Matthew Fornero <mfornero@xxxxxxxxx> wrote:
> Hello All,
>
> I am working on IEEE 802.3 testing for a system with two Intel
> gigabit Ethernet controllers (82577 and 82574), and am currently looking
> into transmitter distortion testing (40.6.1.2.4). One of the controllers
> (82577) narrowly (but consistently) passes this test (< 10 mV distortion).
> While the other (82574) consistently fails (~16 mV distortion). My power
> supplies and clocks appear to be good, and the clearance from the MDI lines
> to any aggressors appears good as well.
>
> Looking at the sample waveforms output from the two controllers in test
> mode 4, there are some slight differences (maybe some extra attenuation of
> the high frequency components for the 82574), but given the way that
> gigabit Ethernet transmits, it's hard to determine what the "ideal"
> waveform is.
>
> My initial idea is that it may be something in the MDI traces, though I'm
> not sure exactly what. The traces are fairly short (30 - 50 mm; Intel's
> design guides recommend < 100 mm) and are matched to within 0.25 mm (10
> mils).
> Both controllers use internal termination, and both are routed entirely as
> microstrips (82674 on the bottom of the board, 82577 on the top) so there
> are no/minimal stubs.
>
> My initial thoughts:
> 1) The MDI traces are routed as 95 Ohm differential pairs (55 ohm single
> ended), with +/- 10% controlled impedance fabrication. This deviation from
> 100/50 was due to space constraints, but should be acceptable based on
> Intel's design guide. The guide calls out 100 Ohm +/- 15%, but specifically
> allows 95 Ohm +/- 10%. One concern I have is that the Intel design guide
> recommends using the 100kHz - 100 MHz relative permittivity (Er) value for
> the dielectric rather than the traditional 1 Ghz value for calculating a
> stackup-- which I believe my fab house failed to do. They do, however,
> measure the actual impedance via TDR, so maybe this is not an issue?
>
> 2) I am using a TE (Tyco) MagJack for my connector/magnetics with through
> hole leads. For the controller on the bottom (82577-- which passes
> narrowly), there should be no/minimal stub. For the controller on the top
> (82574), there will be a ~3.5 mm stub just before the magnetics. Maybe this
> is contributing to the issue?
>
> Any thoughts on this, or suggestions of an area I should be investigating?
>
> Best Regards,
> Matthew Fornero
>
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