Andy Henson schrieb: > Does anyone have any figures for network performance which the EP93xx > family can achieve? > > I am considering it for a project where the application would need to > stream a lot of data out of the ethernet port. (The goal is around > 6MB/sec). > > Andy Henson > Hello Andy, don't forget to look into the errata sheet. I switched to 10 MBIT half duplex to prevent a network failure with our custom board. :-/ BTW, I have a high load, bad network irq latency and that seems be the reason. Currently I use the implementation from cirrus - I could be that the mainline kernel version works better, but I am not sure. I think for tests you should evaluate both versions (mainline and cirrus). Br, Harald Errata vom Cirrus: http://www.cirrus.com/en/pubs/errata/ER653E2B.pdf When there is inadequate AHB bus bandwidth for data to be transferred from the Ethernet controller FIFO to the receive descriptor, the Ethernet FIFO will overflow and cause the Ethernet controller to fail to receive any more packets. This problem will also occur if the processor is too busy to service incoming packets in a timely manner. By the time that new receive descriptors are available, the data in the FIFO will contain frames that are corrupted. It is the job of the system designer to ensure that there is adequate bandwidth for the applications being run. Workaround This is a rare occurrence, however at a system level it is important to reserve adequate bandwidth for the Ethernet controller. This can be accomplished by some of the following: - Reducing the bandwidth use of other bus masters in the system. - Lowering Ethernet rate to half duplex or 10Mbit if higher bandwidth is not required. - Ensuring that the Ethernet controller receive descriptor processing is given a high enough priority to ensure that the controller never runs out of receive descriptors. -- Harald Krammer Brucknerstrasse 33 A - 4020 Linz AUSTRIA Mobil +43.(0) 664. 130 59 58 Mail: Harald.Krammer (at) hkr.at