[PCB_FORUM] Re: Prop Delay question....
- From: Kevin McCowan <kmccowan@xxxxxxxxxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Thu, 03 Mar 2005 10:40:33 -0500
They were generated using list element (it says
so at the top of the listing).
You seem to want something other than that.
Have you checked reports? I have specctra running
right now and cannot do it myself.
Kevin McCowan
Sr. PCB Designer
TSI Telsys
Gene Carman wrote:
Is there a simple way to get a prop delay report in 15.2... I have an engineer that wants the capacitance and prop delay on address and data lines and frankly I have not read the manual on this section.
How was the report below generated.
Thanks
-----Original Message-----
From: Dave Seymour [mailto:deseymour-pcb@xxxxxxxxxxxxx]
Sent: Wednesday, March 02, 2005 2:58 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Prop Delay not seeing all the net
15.2
Anyone know why a DRC is generated when the entire
net length is correct?
The net length is supposed to be between 2000 and 2500 mils.
Probing the net gives --->Total Etch Length: 2280.31 MIL.
Very good.
When the DRC is probed, only a portion of the net is reported.
Actual value: 1032.65 MIL
Very Bad.
What up with that?
I did check the box for in the user setup for pre 11.x checking.
Thanks for the help.
dave
LISTING: 1 element(s)
< NET >
Net Name: CPU_CLK6
Via Count: 3
Total Etch Length: 2280.31 MIL
Total Manhattan Length: 2257.7 MIL
Percent Manhattan: 101.00%
Pin Type SigNoise Model
--- ---- --------------
R93.2 BI CDSDefaultIO
J5.A13 BI CDSDefaultIO
U4.27 IN CDSDefaultInput
No connections remaining
Properties attached to net
CLASS = CPU_CLK
NET_SPACING_TYPE = CLOCK
NO_GLOSS
MANUAL_ROUTES
PROPAGATION_DELAY = AD:AR:2000 MIL:2500 MIL
LISTING: 1 element(s)
< DRC ERROR >
Class: DRC ERROR CLASS
Subclass: ALL
Origin xy: (2083.30 -790.00)
CONSTRAINT: Propagation Delay
CONSTRAINT SET: PROPAGATION_DELAY
CONSTRAINT TYPE: ATTRIBUTE
Constraint value: AD:AR:2000 MIL:2500 MIL
Actual value: 1032.65 MIL
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