[PCB_FORUM] Re: Multi-GB topology
- From: "David Greig" <david@xxxxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Wed, 20 Apr 2005 20:14:54 +0100
Hi Andrew
Concept is to implement coupled tlines in the z dimension.
Most of the HS connector manufacturers have reasonable reference literature
and models, occasionally even S-params available from fixtured measurements
if asked. Their recommendations are a good starting point.
A 3D field solver, a wee(*) bit of tline knowledge and designer imagination
always seems to work.
SQ 630 does have a true 3D facility, and there are a few other good ones out
there that can be used for pre-route strategy and post route verification.
Occasionally it is better to revert to "uncoupled" pairs for return path
integrity, but 2.5mm/1.5mm and even 2mm pitch connectors normally seem best
kept coupled (oval voids in planes). 1mm arrays usually become a pain above
a few GHz. Normally boils down to managing slew and skew to retain UI
timing, and cross coupling and return paths for most everything else. There
are a few tline tweaks that can be made to obviate discontinuities from
via's and holes.
At the higher end, say above 3G, HF loss becomes the dominant factor with
longer spans. The only sane thing is to model and verify design intent thru
simulation.
Funny thing is that after a while, you end up with a bunch of topologies and
simulation becomes just an additional task needing an expensive tool to
check those bits where compromise was necessary due to fabrication and cost
requirements.
* Scottish "wee" - an ambiguous expression used by a Northern tribe to
describe any amount of a whole bunch of anything
Best Regards
David Greig
______________________________
GigaDyne Ltd
Buchan House
Carnegie Campus
Dunfermline KY11 8PL
United Kingdom
t: +44 (0)1383 624 975
http://www.gigadyne.co.uk <http://www.gigadyne.co.uk/>
______________________________
_____
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Andrew Noonan
Sent: 2005-April-20 19:00
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Multi-GB topology
With ever-increasing bit rates on high speed links, how are other designers
dealing with some of the more complex editing of planes for parasitic
capacitance reduction? Many connector manufacturers are suggesting things
like 'dog-bone' shaped voids or rectangular voids encompassing both true and
compliment of a differential pair.
Is this something that's on the roadmap for future versions of Allegro?
Do some of you make the edits in Allegro?
Do some of you use post-processing tools to make the edits?
Thanks for you help,
Andrew Noonan
Sr. PCB Designer
Topspin Communications
(w)650-316-3398
(c)650-814-3677
--
Virus scanned by Lumison.
Other related posts:
