[PCB_FORUM] Diff Pair behavior ... They are right, but they are wrong too ???

Hey Allegro-ers,

I'm getting some odd behavior with Diffs in 15.2.  I may be confusing myself
with how it was handled in v14???   I have the primary width and gap as well
as neck width and gap set in the constraint manager. I need to have a diff
to diff separation as well.  I have that as a line to line spacing in a
Net_Spacing_Type and have the assignment table correct.  When I route the
diffs, the correct line widths and gap (primary and necking) appears.  As
soon as I finish the route, DRCs pop up all over the place with a line-line
violation.  The diffs are routed correctly, but the DRC says is should be
the line to line spacing from the line-line set in the net_spacing_type.

Why am I getting DRCs if all is correct as defined in the constraint manager
and how do you control the diff to diff min spacing?

Thanks to all in advance!
-Randy




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