[ibis-interconn] Re: Interpretation of [Component] [Pin] signal_name
- From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
- To: IBIS-Interconnect <ibis-interconn@xxxxxxxxxxxxx>
- Date: Fri, 19 Sep 2014 23:18:16 +0000
Walter,
That new rule is something we can consider. So to summarize, the need
for this new rule would be to prevent the possibility to make models
in which the [Pin] keyword has identical signal names in the 2nd column
(for example Vcc), while the [Pin Mapping] keyword defines independent
bus labels for the same pins (for example Vcc1, Vcc2, Vcc3, etc...).
Currently the IBIS specification allow this situation, making the signal
name column of the [Pin] keyword somewhat meaningless as far as the netlist
generation goes.
So the next question I want to ask then is why is this change necessary
in light of the new package/interconnect proposal? Is that because you
want to be able to make use of the signal name under the [Pin] keyword
for netlisting (connectivity definition) purposes?
Also a small detail question: This new rule would only be for the power
and ground pins, right? For signal pins you would still allow identical
signal names in the 2nd column of the [Pin] keyword, even if they are
associated with totally independent signals, and buffer models, correct?
Thanks,
Arpad
============================================================================
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Friday, September 19, 2014 5:49 PM
To: IBIS-Interconnect
Subject: [ibis-interconn] Re: Interpretation of [Component] [Pin] signal_name
Arpad,
I think that the IBIS specification by defining signal_name as the Pinout
"Name" implies by the most logical inference that all of the Pins that have the
same Pinout Name should connect to the same CAD Net (or CAD Nets).
It may be possible that VDD is the data book name for 100 pins, but in
actuality 30 of the VDD pins are supplied by one 3V supply "A" and 70 are
supplied by a second 3V supply "B". And let us also assume that there are 50
buffers in the chip and 20 use Power_Clamp_Reference A, and 30 use
Power_Clamp_Reference B. So pin mapping uses two bus names for VDD (e.g. VDDA
and VDDB). VDDA is the reference on the 30 "A" Pins, and 20 "A" I/O buffers,
and VDDB is the reference for the 70 "B" Pins, and 30 "B" I/O buffers.
It is currently legal in Pin Mapping to create a Bus Name "VDS" with a POWER
Pin with signal_name VDD and a POWER Pin with singal_name VCC. This is
currently interpreted in [Pin Mapping] that the VDD power pin and the VCC power
pin are shorted together, and that this shorted VDD/VSS is the Reference
voltage on any buffer instance that uses Bus Name "VDS".
So if you accept the accepted definition of Data Book Name, then it is only
natural to add the following rule to be applied to Pin Mapping Bus Labels.
New Rules
All POWER and GND pins that have the same "bus label" must have the same
signal_name.
If this rule was added to IBIS, then every Buffer Reference references a Bus
Label that references a single signal_name.
The current Interconnect Modeling BIRD allows the model maker to create a 150
terminal interconnect subckt for the detailed analysis of this power delivery.
Users do not get easy access to such complex power distribution models and
might get some simple package power delivery model that assumes all of the VDD
pins are shorted together and all of the VDD buffer terminals are shorted
together. One possible enhancement to the Interconnect Model Terminal section
is to allow a "Bus Label" to be associated with a terminal.
Walter
From:
ibis-interconn-bounce@xxxxxxxxxxxxx<mailto:ibis-interconn-bounce@xxxxxxxxxxxxx>
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Muranyi, Arpad
Sent: Friday, September 19, 2014 5:06 PM
To: IBIS-Interconnect
Subject: [ibis-interconn] Re: Interpretation of [Component] [Pin] signal_name
Walter,
Could you please clarify what you mean by "same voltage (within some
tolerance)":
"I believe that this means ... that two pins with model POWER or GND that have
the same signal_name have the same voltage (within some tolerance)."?
The question we are trying to find an answer to is how you interpret the 2nd
column
of the [Pin] keyword in the existing IBIS spec. This is an important point
because
it is strongly tied to the question of how [Pin Mapping] works and whether we
will
have to make [Pin Mapping] mutually exclusive with the new package/interconnect
proposal or whether we can make them work together.
So do you think of the signal name in [Pin] as a piece of "decorative"
information,
or do you think of it as a node name or signal name of some sort which is to be
used in generating netlists with descriptions of connections (shorts) between
those
items which have the same name?
Thanks,
Arpad
======================================================================================
From:
ibis-interconn-bounce@xxxxxxxxxxxxx<mailto:ibis-interconn-bounce@xxxxxxxxxxxxx>
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Thursday, September 18, 2014 4:05 PM
To: IBIS-Interconnect
Subject: [ibis-interconn] FW: Interpretation of [Component] [Pin] signal_name
All,
In the IBIS Interconnect committee there is a discussion on the meaning of
signal_name (second column in the [Component]/[Pin] record). The first column
is pin_name (aka component "Pin Number"), and the second column is signal_name.
On page 21 of IBIS 6.0:
"The second column, signal_name, gives the data book name for the signal on
that pin."
In the data book (data sheet) for an electronic component there is a Pinout
section which lists for each Pin the Pin Number and Name. I want to focus on a
specific example of a component having two pins with the name in the data book
"VDD". The data book will also give a nominal voltage for VDD (e.g. 3.0 +/-.1
Volts). These voltages are referenced to another Pinout Name (e.g. "VSS"). I
claim that this means the PCB must supply 3.0 +/-.1 Volts to both of these
pins. The power distribution on the PCB, and within the package and chip can be
complex, therefore one cannot assume that the voltage at each of these two pins
are the same, but I claim that the voltage difference between these two pins
must be less than .2 Volts (although the data book may have additional
constraints on this difference).
I believe that this means (although not explicitly stated) in the IBIS spec
that two pins with model POWER or GND that have the same signal_name have the
same voltage (within some tolerance).
Walter
Walter Katz
wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>
Phone 303.449-2308
Mobile 303.335-6156
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