[ibis-interconn] IBIS Ad Hoc Interconnect Task Group May 27 Minutes and June 9 reminder

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IBIS INTERCONNECT MODELING AD HOC TASK GROUP MEETING MINUTES AND AGENDA

http://www.eda.org/ibis/adhoc/interconnect/

Mailing list: ibis-interconn@xxxxxxxxxxxxx

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Next Meeting
Wednesday, June 9, 2009
8 AM US Pacific Time

               Telephone     Bridge   Passcode
              916-356-2663     5      192-4067

(for international and alternate US numbers, contact Michael Mirmak)

LiveMeeting: https://webjoin.intel.com/?passcode=1924067

Agenda:
- Call for patents
- Opens
- Review of draft format for sparse network representation

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Minutes from May 20:

Attendees:
----------
(* denotes present)
Agilent                    - Radek Biernacki, John Moore, Ken Wong
Ansoft                     - Denis Soldo
Cadence Design Systems     - Terry Jernberg, Brad Griffin
Cisco Systems              - Mike LaBonte
Green Streak Programs      - Lynne Green
Hewlett-Packard            - Rob Elliott
Intel                      - Michael Mirmak*
Mentor Graphics Corp.      - John Angulo*, Vladimir Dmitriev-Zdorov*
Micron Technology          - Randy Wolff
Sigrity                    - Sam Chitwood, Raymond Y. Chen, Tao Su, Brad Brim*
SiSoft                     - Walter Katz*
Teraspeed Consulting Group - Bob Ross*

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No patents were declared.

Michael raised the issue of the GNU General Public License and whether an
explicit prohibition should be enforced on it in the Touchstone 2.0 parser
bid packet.  John suggested that language specify the 3 separate variations
of GPL, but the fully viral and partially viral aspects are the major concern.
Bob suggested that the language specify that whatever code is provided needs
to be fully and privately redistributable.

Michael will add a statement regarding a prohibition on GNU GPL to the
bid packet.

Michael asked about C++ support.  John observed that, in the 1990s, the C++
language was not necessarily 100% compatible/portable.  This is not so much
of a problem today.

Michael asked whether the team had any objections to allowing it.  Bob stated
that he no issue.  Michael will edit the document to include C++ support.

Walter provided an overview of a sparse matrix treatment, using a 300-pin
connector as an example.  Walter mentioned RLGC length limitations as a
fundamental problem with usage of W-element-style representations for
connectors.

The team discussed the various methods for implementing sparse matrix data
reduction.  Brad stated that eliminating redundant information is the objective.
This includes removing redundant data but perhaps not removing "zero" data or
treating redundant data as zero.

Vladimir responded that the discussion seems to narrow the scope of things
represented in the standard.  Connectors are a specific application.  Bondwires
are another application, with intermediate ports.  The problem is more 
complicated
than just a two-sided arrangement.  One complex application example is power
integrity: it would be nice to have a general approach, for all these kinds of 
applications.

Michael noted, for illustration, that the representation of connectors and
interconnects for PCB SI is the #1 issue hitting the participants in the 
meeting.

Brad stated that data removal is the bigger issue, adding that he supports
Vladimir's reduction/presentation approach.  Decisions about thresholding
of significant vs. insignificant data are very hard.

Michael will assemble some simple proposals for spare matrix representations.

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