Bob,
Is this a real model with no GND Clamp, or is this a make believe model of
what IBIS can do but no one really would?
As for your statement
The main point is that Vinh, Vinl and Vmeas are always
entered and checked with respect to the external reference
- as if the reference voltage used for device under test were
shifted.
I again reject this interpretation of the standard, and I object to you
repeatedly stating this. Nowhere in the standard does it say this. These
are levels that only apply when the device is running in the DUT
conditions. And your statement "- as if the reference voltage used for
device under test were shifted." is ambiguous.
I asked the questions below so that we can unambiguously understand how to
apply IBIS measurement thresholds to simulation generated voltages. I will
not be able to proceed without the answers to these questions, and without
myself and others agreeing to a set of answers to all of these questions.
Walter
From: Bob Ross [mailto:bob@xxxxxxxxxxxxxxxxx] ;
Sent: Friday, April 15, 2016 7:19 PM
To: wkatz@xxxxxxxxxx; ibis-editorial@xxxxxxxxxxxxx
Subject: RE: [ibis-editorial] Re: Comparing simulated Vpad with VinL
Walter,
I can't answer all the questions at this time, but attached is
a correct model with correct PECL levels and with [Pin Mapping].
Some Cautions are issued for legal connections to be sure
that the connections were what was intended.
The main point is that Vinh, Vinl and Vmeas are always
entered and checked with respect to the external reference
- as if the reference voltage used for device under test were
shifted.
Therefore, for PECL the values are used:
[Model] PECL_5V
Model_type I/O_ECL
Vinh = 3.87V
Vinl = 3.52V
|
Vmeas = 3.71
Rref = 50.0
Cref = 0.0
Vref = 3.0
Note, because there is no [GND Clamp], I can set its
[GND Clamp Reference] to any value and still have a
legal IBIS model - as a pathological but not-for-shipping
test case.
The EDA tool can provide the rail voltages externally,
within a limited range, but all of the Spec information
is still fixed.
Several EDA tools test and display correctly the Vinh, Vinl,
and Vmeas information as dashed lines on top of actual
simulations based on the information given in these
buffers.
Bob
From: ibis-editorial-bounce@xxxxxxxxxxxxx
<mailto:ibis-editorial-bounce@xxxxxxxxxxxxx>
[mailto:ibis-editorial-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Friday, April 15, 2016 3:43 PM
To: Bob Ross; ibis-editorial@xxxxxxxxxxxxx
<mailto:ibis-editorial@xxxxxxxxxxxxx>
Subject: [ibis-editorial] Re: Comparing simulated Vpad with VinL
Bob,
Please correct your test case so that the ECL_0V model has the ECL levels,
not the PECL levels.
Also, can you correct the IV curves so that we do not get the following
errors:
ERROR - Model PECL_5V: The [Rising Waveform]
with [R_fixture]=50 Ohms and [V_fixture]=-2V
has TYP column DC endpoints of -1.81V and -0.92v, but
an equivalent load applied to the model's I-V tables yields
different voltages ( 2.64V and 3.51V),
a difference of 510.65% and 508.59%, respectively.
ERROR - Model PECL_5V: The [Falling Waveform]
with [R_fixture]=50 Ohms and [V_fixture]=-2V
has TYP column DC endpoints of -1.81V and -0.92v, but
an equivalent load applied to the model's I-V tables yields
different voltages ( 2.64V and 3.51V),
a difference of 510.65% and 508.59%, respectively.
Second please add a [Pin Mapping] section using the IBIS 6.1 requirements:
I would then like the answers to the questions below when the device is
run in the following two conditions:
1. 0.1V supplied to pin 4 (relative to a simulator Node 0), and 5.4V
supplied to pin 3 (relative to a simulator Node 0).
2. -5.1V supplied to pin 4 (relative to a simulator Node 0), and
0.2V supplied to pin 3 (relative to a simulator Node 0).
With the buffers driving
1. What are the Vmeas at pins 1 and 2 (relative to a simulator Node
0) that are used for standard load timing?
2. When the voltages at pins 1 and 2 (relative to a simulator Node
0) are these Vmeas:
a. What is the current flowing through pins 1 and 2 when the buffer
is in the low state?
i.
Please give the details of what voltage value is applied to each IV curve
b. What is the current flowing through pins 1 and 2 when the buffer
is in the high state?
i.
Please give the details of what voltage value is applied to each IV curve
With the buffers receiving
1. What are the Vinl and Vinh at pins 1 and 2 (relative to a
simulator Node 0) that are used for determining if the buffer is in the
guaranteed low state, and the guaranteed high state.
2. When the voltages at pins 1 and 2 (relative to a simulator Node
0) are these Vinl and Vinh:
a. What is the current flowing through pins 1 and 2?
i.
Please give the details of what voltage value is applied to each IV curve
Walter
From: Bob Ross [mailto:bob@xxxxxxxxxxxxxxxxx] ;
Sent: Friday, April 15, 2016 1:54 PM
To: wkatz@xxxxxxxxxx <mailto:wkatz@xxxxxxxxxx> ;
ibis-editorial@xxxxxxxxxxxxx <mailto:ibis-editorial@xxxxxxxxxxxxx>
Subject: RE: [ibis-editorial] Comparing simulated Vpad with VinL
All,
I did not follow all the rules, but IBIS must address all cases,
whether or not any vendor chooses to support them for
business reasons.
The attached file, which issues Warnings and Error, shows
the impact of making a revised interpretation than currently
checked by ibischk6.
I have attached a test case that fails if we follow literally some
of the statements. The issue of voltage references apply
not only to [Voltage Range], [* References], and also
Vmeas, V_fixture, and the [Rising Waveform] and [Falling Waveform]
entries and for Vinl and Vinh and all the [Model Spec]
voltage entries.
We need to be careful not to break many existing models
that are issued by IC vendors and supported by many tools.
Bob
From: <mailto:ibis-editorial-bounce@xxxxxxxxxxxxx>
ibis-editorial-bounce@xxxxxxxxxxxxx [
<mailto:ibis-editorial-bounce@xxxxxxxxxxxxx>
mailto:ibis-editorial-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Friday, April 15, 2016 10:26 AM
To: <mailto:ibis-editorial@xxxxxxxxxxxxx> ibis-editorial@xxxxxxxxxxxxx
Subject: [ibis-editorial] Comparing simulated Vpad with VinL
All,
When determining Vpad to an IBIS threshold value (e.g. VinL) we do the
following:
1. When only [Voltage Range] is specified or [Pulldown
Reference]=[GND Clamp Reference]=0. (assumes Pdref=Gcref)
a. Compare (Vpad-gcref) to the value of VinL
b. One might argue that this is really a function of (Vpad-gcref) and
(Pcref-Gcref) and (Puref- Gcref), but IBIS does not tell you that either.
2. When [Pulldown Reference]=[GND Clamp Reference]=DUT_Reference !=
0. (assumes Pdref=Gcref)
a. Compare (Vpad-(gcref- DUT_Reference)) to the value of VinL
3. When [Pulldown Reference] != [GND Clamp Reference] (Pdref !=
Gcref)
a. Can do one of two things
i.
Compare (Vpad-(gcref- [GND Clamp Reference] )) to the value of VinL
ii.
Compare (Vpad-(pdref- [Pulldown Reference] )) to the value of VinL
All SiSoft cares about is 1. Bob's answer to 2 and 3 is to generate
multiple models with different values of [Pulldown Reference] and [GND
Clamp Reference] for each condition that he plans to simulate with these
models.
IBIS is silent on the answer to 3. I point out that since there does not
seem to exist a case in nature (other than IBIS allows it), I think it
will be impossible to find out which is correct 3.a.i or 3.a.ii, since
nobody has ever made (or plans to make) such an I/O buffer.
I feel I am wasting my time in these meetings by trying to resolve what to
do for item 3, and I suggest that we simply state that although IBIS
allows this impossible construct, we leave it up to the User/EDA tool on
how do handle measurement thresholds. We do this already for VinL and VinH
(are they fixed voltage (relative to the local Pdref and Gcref) or are
they really meant to represent percentage of the voltage swing.
I hope that MM's introductory paragraph on this will let us move on.
Walter
Walter Katz
<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx
Phone 303.449-2308
Mobile 303.335-6156
