[hellogcc] [patch 6 md.texi]: Update gccint-zh trunk to upstreams r179462
- From: Yao Qi <qiyaoltc@xxxxxxxxx>
- To: hellogcc@xxxxxxxxxxxxx
- Date: Fri, 7 Oct 2011 22:09:58 +0800
On Fri, Oct 07, 2011 at 09:47:15PM +0800, Yao Qi wrote:
> 这个patch是fsf gcc doc目录下边和gccint有关文件从 r170935到
> r179462的修改。我们gccint-zh trunk也是根据这个patch进行修改。
>
> --
> Yao Qi <qiyaoltc AT gmail DOT com>
>
> Index: md.texi
> ===================================================================
> --- md.texi (revision 170935)
> +++ md.texi (revision 179462)
> @@ -1773,37 +1773,9 @@
>
> @item Q
> A memory address based on Y or Z pointer with displacement.
> -@end table
>
> -@item CRX Architecture---@file{config/crx/crx.h}
> -@table @code
> -
> -@item b
> -Registers from r0 to r14 (registers without stack pointer)
> -
> -@item l
> -Register r16 (64-bit accumulator lo register)
> -
> -@item h
> -Register r17 (64-bit accumulator hi register)
> -
> -@item k
> -Register pair r16-r17. (64-bit accumulator lo-hi pair)
> -
> -@item I
> -Constant that fits in 3 bits
> -
> -@item J
> -Constant that fits in 4 bits
> -
> -@item K
> -Constant that fits in 5 bits
> -
> -@item L
> -Constant that is one of @minus{}1, 4, @minus{}4, 7, 8, 12, 16, 20, 32, 48
> -
> -@item G
> -Floating point constant that is legal for store immediate
> +@item C04
> +Constant integer 4
> @end table
>
> @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
> @@ -1998,7 +1970,7 @@
> three instructions
>
> @item m
> -Memory operand.
> +Memory operand.
> Normally, @code{m} does not allow addresses that update the base register.
> If @samp{<} or @samp{>} constraint is also used, they are allowed and
> therefore on PowerPC targets in that case it is only safe
> @@ -2173,7 +2145,7 @@
> 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
>
> @item N
> -Unsigned 8-bit integer constant (for @code{in} and @code{out}
> +Unsigned 8-bit integer constant (for @code{in} and @code{out}
> instructions).
>
> @ifset INTERNALS
> @@ -2868,64 +2840,6 @@
>
> @end table
>
> -@item Motorola 68HC11 & 68HC12 families---@file{config/m68hc11/m68hc11.h}
> -@table @code
> -@item a
> -Register `a'
> -
> -@item b
> -Register `b'
> -
> -@item d
> -Register `d'
> -
> -@item q
> -An 8-bit register
> -
> -@item t
> -Temporary soft register _.tmp
> -
> -@item u
> -A soft register _.d1 to _.d31
> -
> -@item w
> -Stack pointer register
> -
> -@item x
> -Register `x'
> -
> -@item y
> -Register `y'
> -
> -@item z
> -Pseudo register `z' (replaced by `x' or `y' at the end)
> -
> -@item A
> -An address register: x, y or z
> -
> -@item B
> -An address register: x or y
> -
> -@item D
> -Register pair (x:d) to form a 32-bit value
> -
> -@item L
> -Constants in the range @minus{}65536 to 65535
> -
> -@item M
> -Constants whose 16-bit low part is zero
> -
> -@item N
> -Constant integer 1 or @minus{}1
> -
> -@item O
> -Constant integer 16
> -
> -@item P
> -Constants in the range @minus{}8 to 2
> -
> -@end table
> -
> @item Moxie---@file{config/moxie/constraints.md}
> @table @code
> @item A
> @@ -3111,70 +3025,70 @@
> @item SPU---@file{config/spu/spu.h}
> @table @code
> @item a
> -An immediate which can be loaded with the il/ila/ilh/ilhu instructions.
> const_int is treated as a 64 bit value.
> +An immediate which can be loaded with the il/ila/ilh/ilhu instructions.
> const_int is treated as a 64 bit value.
>
> @item c
> -An immediate for and/xor/or instructions. const_int is treated as a 64 bit
> value.
> +An immediate for and/xor/or instructions. const_int is treated as a 64 bit
> value.
>
> @item d
> -An immediate for the @code{iohl} instruction. const_int is treated as a 64
> bit value.
> +An immediate for the @code{iohl} instruction. const_int is treated as a 64
> bit value.
>
> @item f
> -An immediate which can be loaded with @code{fsmbi}.
> +An immediate which can be loaded with @code{fsmbi}.
>
> @item A
> -An immediate which can be loaded with the il/ila/ilh/ilhu instructions.
> const_int is treated as a 32 bit value.
> +An immediate which can be loaded with the il/ila/ilh/ilhu instructions.
> const_int is treated as a 32 bit value.
>
> @item B
> -An immediate for most arithmetic instructions. const_int is treated as a 32
> bit value.
> +An immediate for most arithmetic instructions. const_int is treated as a 32
> bit value.
>
> @item C
> -An immediate for and/xor/or instructions. const_int is treated as a 32 bit
> value.
> +An immediate for and/xor/or instructions. const_int is treated as a 32 bit
> value.
>
> @item D
> -An immediate for the @code{iohl} instruction. const_int is treated as a 32
> bit value.
> +An immediate for the @code{iohl} instruction. const_int is treated as a 32
> bit value.
>
> @item I
> -A constant in the range [@minus{}64, 63] for shift/rotate instructions.
> +A constant in the range [@minus{}64, 63] for shift/rotate instructions.
>
> @item J
> -An unsigned 7-bit constant for conversion/nop/channel instructions.
> +An unsigned 7-bit constant for conversion/nop/channel instructions.
>
> @item K
> -A signed 10-bit constant for most arithmetic instructions.
> +A signed 10-bit constant for most arithmetic instructions.
>
> @item M
> -A signed 16 bit immediate for @code{stop}.
> +A signed 16 bit immediate for @code{stop}.
>
> @item N
> -An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
> +An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
>
> @item O
> -An unsigned 7-bit constant whose 3 least significant bits are 0.
> +An unsigned 7-bit constant whose 3 least significant bits are 0.
>
> @item P
> -An unsigned 3-bit constant for 16-byte rotates and shifts
> +An unsigned 3-bit constant for 16-byte rotates and shifts
>
> @item R
> -Call operand, reg, for indirect calls
> +Call operand, reg, for indirect calls
>
> @item S
> -Call operand, symbol, for relative calls.
> +Call operand, symbol, for relative calls.
>
> @item T
> -Call operand, const_int, for absolute calls.
> +Call operand, const_int, for absolute calls.
>
> @item U
> -An immediate which can be loaded with the il/ila/ilh/ilhu instructions.
> const_int is sign extended to 128 bit.
> +An immediate which can be loaded with the il/ila/ilh/ilhu instructions.
> const_int is sign extended to 128 bit.
>
> @item W
> -An immediate for shift and rotate instructions. const_int is treated as a
> 32 bit value.
> +An immediate for shift and rotate instructions. const_int is treated as a
> 32 bit value.
>
> @item Y
> -An immediate for and/xor/or instructions. const_int is sign extended as a
> 128 bit.
> +An immediate for and/xor/or instructions. const_int is sign extended as a
> 128 bit.
>
> @item Z
> -An immediate for the @code{iohl} instruction. const_int is sign extended to
> 128 bit.
> +An immediate for the @code{iohl} instruction. const_int is sign extended to
> 128 bit.
>
> @end table
>
> @@ -3390,6 +3304,89 @@
>
> @end table
>
> +@item TI C6X family---@file{config/c6x/constraints.md}
> +@table @code
> +@item a
> +Register file A (A0--A31).
> +
> +@item b
> +Register file B (B0--B31).
> +
> +@item A
> +Predicate registers in register file A (A0--A2 on C64X and
> +higher, A1 and A2 otherwise).
> +
> +@item B
> +Predicate registers in register file B (B0--B2).
> +
> +@item C
> +A call-used register in register file B (B0--B9, B16--B31).
> +
> +@item Da
> +Register file A, excluding predicate registers (A3--A31,
> +plus A0 if not C64X or higher).
> +
> +@item Db
> +Register file B, excluding predicate registers (B3--B31).
> +
> +@item Iu4
> +Integer constant in the range 0 @dots{} 15.
> +
> +@item Iu5
> +Integer constant in the range 0 @dots{} 31.
> +
> +@item In5
> +Integer constant in the range @minus{}31 @dots{} 0.
> +
> +@item Is5
> +Integer constant in the range @minus{}16 @dots{} 15.
> +
> +@item I5x
> +Integer constant that can be the operand of an ADDA or a SUBA insn.
> +
> +@item IuB
> +Integer constant in the range 0 @dots{} 65535.
> +
> +@item IsB
> +Integer constant in the range @minus{}32768 @dots{} 32767.
> +
> +@item IsC
> +Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
> +
> +@item Jc
> +Integer constant that is a valid mask for the clr instruction.
> +
> +@item Js
> +Integer constant that is a valid mask for the set instruction.
> +
> +@item Q
> +Memory location with A base register.
> +
> +@item R
> +Memory location with B base register.
> +
> +@ifset INTERNALS
> +@item S0
> +On C64x+ targets, a GP-relative small data reference.
> +
> +@item S1
> +Any kind of @code{SYMBOL_REF}, for use in a call address.
> +
> +@item Si
> +Any kind of immediate operand, unless it matches the S0 constraint.
> +
> +@item T
> +Memory location with B base register, but not using a long offset.
> +
> +@item W
> +A memory operand with an address that can't be used in an unaligned access.
> +
> +@end ifset
> +@item Z
> +Register B14 (aka DP).
> +
> +@end table
> +
> @item Xtensa---@file{config/xtensa/constraints.md}
> @table @code
> @item a
> @@ -3524,7 +3521,7 @@
> Machine-specific constraints can be given names of arbitrary length,
> but they must be entirely composed of letters, digits, underscores
> (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
> -must begin with a letter or underscore.
> +must begin with a letter or underscore.
>
> In order to avoid ambiguity in operand constraint strings, no
> constraint can have a name that begins with any other constraint's
> @@ -3935,6 +3932,48 @@
> consecutive memory locations, operand 1 is the first register, and
> operand 2 is a constant: the number of consecutive registers.
>
> +@cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
> +@item @samp{vec_load_lanes@var{m}@var{n}}
> +Perform an interleaved load of several vectors from memory operand 1
> +into register operand 0. Both operands have mode @var{m}. The register
> +operand is viewed as holding consecutive vectors of mode @var{n},
> +while the memory operand is a flat array that contains the same number
> +of elements. The operation is equivalent to:
> +
> +@smallexample
> +int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
> +for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
> + for (i = 0; i < c; i++)
> + operand0[i][j] = operand1[j * c + i];
> +@end smallexample
> +
> +For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
> +from memory into a register of mode @samp{TI}@. The register
> +contains two consecutive vectors of mode @samp{V4HI}@.
> +
> +This pattern can only be used if:
> +@smallexample
> +TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
> +@end smallexample
> +is true. GCC assumes that, if a target supports this kind of
> +instruction for some mode @var{n}, it also supports unaligned
> +loads for vectors of mode @var{n}.
> +
> +@cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
> +@item @samp{vec_store_lanes@var{m}@var{n}}
> +Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
> +and register operands reversed. That is, the instruction is
> +equivalent to:
> +
> +@smallexample
> +int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
> +for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
> + for (i = 0; i < c; i++)
> + operand0[j * c + i] = operand1[i][j];
> +@end smallexample
> +
> +for a memory operand 0 and register operand 1.
> +
> @cindex @code{vec_set@var{m}} instruction pattern
> @item @samp{vec_set@var{m}}
> Set given field in the vector value. Operand 0 is the vector to modify,
> @@ -3947,15 +3986,15 @@
>
> @cindex @code{vec_extract_even@var{m}} instruction pattern
> @item @samp{vec_extract_even@var{m}}
> -Extract even elements from the input vectors (operand 1 and operand 2).
> +Extract even elements from the input vectors (operand 1 and operand 2).
> The even elements of operand 2 are concatenated to the even elements of
> operand
> -1 in their original order. The result is stored in operand 0.
> -The output and input vectors should have the same modes.
> +1 in their original order. The result is stored in operand 0.
> +The output and input vectors should have the same modes.
>
> @cindex @code{vec_extract_odd@var{m}} instruction pattern
> @item @samp{vec_extract_odd@var{m}}
> -Extract odd elements from the input vectors (operand 1 and operand 2).
> -The odd elements of operand 2 are concatenated to the odd elements of
> operand
> +Extract odd elements from the input vectors (operand 1 and operand 2).
> +The odd elements of operand 2 are concatenated to the odd elements of operand
> 1 in their original order. The result is stored in operand 0.
> The output and input vectors should have the same modes.
>
> @@ -3970,7 +4009,7 @@
> @item @samp{vec_interleave_low@var{m}}
> Merge low elements of the two input vectors into the output vector. The
> output
> and input vectors should have the same modes (@code{N} elements). The low
> -@code{N/2} elements of the first input vector are interleaved with the low
> +@code{N/2} elements of the first input vector are interleaved with the low
> @code{N/2} elements of the second input vector.
>
> @cindex @code{vec_init@var{m}} instruction pattern
> @@ -3978,6 +4017,17 @@
> Initialize the vector to given values. Operand 0 is the vector to initialize
> and operand 1 is parallel containing values for individual fields.
>
> +@cindex @code{vcond@var{m}@var{n}} instruction pattern
> +@item @samp{vcond@var{m}@var{n}}
> +Output a conditional vector move. Operand 0 is the destination to
> +receive a combination of operand 1 and operand 2, which are of mode @var{m},
> +dependent on the outcome of the predicate in operand 3 which is a
> +vector comparison with operands of mode @var{n} in operands 4 and 5. The
> +modes @var{m} and @var{n} should have the same size. Operand 0
> +will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
> +where @var{msk} is computed by element-wise evaluation of the vector
> +comparison with a truth value of all-ones and a false value of all-zeros.
> +
> @cindex @code{push@var{m}1} instruction pattern
> @item @samp{push@var{m}1}
> Output a push instruction. Operand 0 is value to push. Used only when
> @@ -4100,17 +4150,17 @@
> @item @samp{sdot_prod@var{m}}
> @cindex @code{udot_prod@var{m}} instruction pattern
> @item @samp{udot_prod@var{m}}
> -Compute the sum of the products of two signed/unsigned elements.
> -Operand 1 and operand 2 are of the same mode. Their product, which is of a
> -wider mode, is computed and added to operand 3. Operand 3 is of a mode equal
> or
> +Compute the sum of the products of two signed/unsigned elements.
> +Operand 1 and operand 2 are of the same mode. Their product, which is of a
> +wider mode, is computed and added to operand 3. Operand 3 is of a mode equal
> or
> wider than the mode of the product. The result is placed in operand 0, which
> -is of the same mode as operand 3.
> +is of the same mode as operand 3.
>
> @cindex @code{ssum_widen@var{m3}} instruction pattern
> @item @samp{ssum_widen@var{m3}}
> @cindex @code{usum_widen@var{m3}} instruction pattern
> @item @samp{usum_widen@var{m3}}
> -Operands 0 and 2 are of the same mode, which is wider than the mode of
> +Operands 0 and 2 are of the same mode, which is wider than the mode of
> operand 1. Add operand 1 to operand 2 and place the widened result in
> operand 0. (This is used express accumulation of elements into an accumulator
> of a wider mode.)
> @@ -4641,8 +4691,9 @@
> string. The instruction is not allowed to prefetch more than one byte
> at a time since either string may end in the first byte and reading past
> that may access an invalid page or segment and cause a fault. The
> -effect of the instruction is to store a value in operand 0 whose sign
> -indicates the result of the comparison.
> +comparison terminates early if the fetched bytes are different or if
> +they are equal to zero. The effect of the instruction is to store a
> +value in operand 0 whose sign indicates the result of the comparison.
>
> @cindex @code{cmpstr@var{m}} instruction pattern
> @item @samp{cmpstr@var{m}}
> @@ -4660,8 +4711,10 @@
> order starting at the beginning of each string. The instruction is not
> allowed
> to prefetch more than one byte at a time since either string may end in the
> first byte and reading past that may access an invalid page or segment and
> -cause a fault. The effect of the instruction is to store a value in operand > 0
> -whose sign indicates the result of the comparison.
> +cause a fault. The comparison will terminate when the fetched bytes
> +are different or if they are equal to zero. The effect of the
> +instruction is to store a value in operand 0 whose sign indicates the
> +result of the comparison.
>
> @cindex @code{cmpmem@var{m}} instruction pattern
> @item @samp{cmpmem@var{m}}
> @@ -4669,9 +4722,10 @@
> of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
> byte by byte in lexicographic order starting at the beginning of each
> block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
> -any bytes in the two memory blocks. The effect of the instruction is
> -to store a value in operand 0 whose sign indicates the result of the
> -comparison.
> +any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
> +the comparison will not stop if both bytes are zero. The effect of
> +the instruction is to store a value in operand 0 whose sign indicates
> +the result of the comparison.
>
> @cindex @code{strlen@var{m}} instruction pattern
> @item @samp{strlen@var{m}}
> @@ -4949,6 +5003,20 @@
> return. Normally, the applicable functions are those which do not need
> to save any registers or allocate stack space.
>
> +It is valid for this pattern to expand to an instruction using
> +@code{simple_return} if no epilogue is required.
> +
> +@cindex @code{simple_return} instruction pattern
> +@item @samp{simple_return}
> +Subroutine return instruction. This instruction pattern name should be
> +defined only if a single instruction can do all the work of returning
> +from a function on a path where no epilogue is required. This pattern
> +is very similar to the @code{return} instruction pattern, but it is emitted
> +only by the shrink-wrapping optimization on paths where the function
> +prologue has not been executed, and a function return should occur without
> +any of the effects of the epilogue. Additional uses may be introduced on
> +paths where both the prologue and the epilogue have executed.
> +
> @findex reload_completed
> @findex leaf_function_p
> For such machines, the condition specified in this pattern should only
> @@ -5294,6 +5362,14 @@
> The @code{prologue} pattern is particularly useful for targets which perform
> instruction scheduling.
>
> +@cindex @code{window_save} instruction pattern
> +@anchor{window_save instruction pattern}
> +@item @samp{window_save}
> +This pattern, if defined, emits RTL for a register window save. It should
> +be defined if the target machine has register windows but the window events
> +are decoupled from calls to subroutines. The canonical example is the SPARC
> +architecture.
> +
> @cindex @code{epilogue} instruction pattern
> @anchor{epilogue instruction pattern}
> @item @samp{epilogue}
> @@ -5510,7 +5586,7 @@
> @cindex @code{stack_protect_set} instruction pattern
> @item @samp{stack_protect_set}
>
> -This pattern, if defined, moves a @code{Pmode} value from the memory
> +This pattern, if defined, moves a @code{ptr_mode} value from the memory
> in operand 1 to the memory in operand 0 without leaving the value in
> a register afterward. This is to avoid leaking the value some place
> that an attacker might use to rewrite the stack guard slot after
> @@ -5521,7 +5597,7 @@
> @cindex @code{stack_protect_test} instruction pattern
> @item @samp{stack_protect_test}
>
> -This pattern, if defined, compares a @code{Pmode} value from the
> +This pattern, if defined, compares a @code{ptr_mode} value from the
> memory in operand 1 with the memory in operand 0 without leaving the
> value in a register afterward and branches to operand 2 if the values
> weren't equal.
> @@ -5887,6 +5963,23 @@
> will be written using @code{zero_extract} rather than the equivalent
> @code{and} or @code{sign_extract} operations.
>
> +@cindex @code{mult}, canonicalization of
> +@item
> +@code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
> +(sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
> +(sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
> +for @code{zero_extend}.
> +
> +@item
> +@code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
> +@var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
> +to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
> +@var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
> +patterns using @code{zero_extend} and @code{lshiftrt}. If the second
> +operand of @code{mult} is also a shift, then that is extended also.
> +This transformation is only applied when it can be proven that the
> +original operation had sufficient precision to prevent overflow.
> +
> @end itemize
>
> Further canonicalization rules are defined in the function
> @@ -6775,6 +6868,14 @@
> @end smallexample
>
> @var{name} is a string specifying the name of the attribute being defined.
> +Some attributes are used in a special way by the rest of the compiler. The
> +@code{enabled} attribute can be used to conditionally enable or disable
> +insn alternatives (@pxref{Disable Insn Alternatives}). The @code{predicable}
> +attribute, together with a suitable @code{define_cond_exec}
> +(@pxref{Conditional Execution}), can be used to automatically generate
> +conditional variants of instruction patterns. The compiler internally uses
> +the names @code{ce_enabled} and @code{nonce_enabled}, so they should not be
> +used elsewhere as alternative names.
>
> @var{list-of-values} is either a string that specifies a comma-separated
> list of values that can be assigned to the attribute, or a null string to
> @@ -6955,6 +7056,30 @@
>
> The @var{constraints} operand is ignored and should be the null string.
>
> +@cindex @code{match_test} and attributes
> +@item (match_test @var{c-expr})
> +The test is true if C expression @var{c-expr} is true. In non-constant
> +attributes, @var{c-expr} has access to the following variables:
> +
> +@table @var
> +@item insn
> +The rtl instruction under test.
> +@item which_alternative
> +The @code{define_insn} alternative that @var{insn} matches.
> +@xref{Output Statement}.
> +@item operands
> +An array of @var{insn}'s rtl operands.
> +@end table
> +
> +@var{c-expr} behaves like the condition in a C @code{if} statement,
> +so there is no need to explicitly convert the expression into a boolean
> +0 or 1 value. For example, the following two tests are equivalent:
> +
> +@smallexample
> +(match_test "x & 2")
> +(match_test "(x & 2) != 0")
> +@end smallexample
> +
> @cindex @code{le} and attributes
> @cindex @code{leu} and attributes
> @cindex @code{lt} and attributes
> @@ -7711,8 +7836,16 @@
>
> @var{number} defines when the result generated by the instructions
> given in string @var{out_insn_names} will be ready for the
> -instructions given in string @var{in_insn_names}. The instructions in
> -the string are separated by commas.
> +instructions given in string @var{in_insn_names}. Each of these
> +strings is a comma-separated list of filename-style globs and
> +they refer to the names of @code{define_insn_reservation}s.
> +For example:
> +@smallexample
> +(define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
> +@end smallexample
> +defines a bypass between instructions that start with
> +@samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
> +@samp{cpu1_load_}.
>
> @var{guard} is an optional string giving the name of a C function which
> defines an additional guard for the bypass. The function will get the
> @@ -7808,7 +7941,7 @@
> unit in the first string can be reserved only if each pattern of units
> whose names are in the second string is not reserved. This is an
> asymmetric relation (actually @samp{exclusion_set} is analogous to
> -this one but it is symmetric). For example it might be useful in a
> +this one but it is symmetric). For example it might be useful in a
> @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
> after either @samp{slot1} or @samp{slot2} have been reserved. This
> can be described as:
> @@ -7870,6 +8003,13 @@
> non-critical errors.
>
> @item
> +@dfn{no-comb-vect} prevents the automaton generator from generating
> +two data structures and comparing them for space efficiency. Using
> +a comb vector to represent transitions may be better, but it can be
> +very expensive to construct. This option is useful if the build
> +process spends an unacceptably long time in genautomata.
> +
> +@item
> @dfn{ndfa} makes nondeterministic finite state automata. This affects
> the treatment of operator @samp{|} in the regular expressions. The
> usual treatment of the operator is to try the first alternative and,
> @@ -7878,6 +8018,16 @@
> may be rejected by reservations in the subsequent insns.
>
> @item
> +@dfn{collapse-ndfa} modifies the behaviour of the generator when
> +producing an automaton. An additional state transition to collapse a
> +nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
> +state is generated. It can be triggered by passing @code{const0_rtx} to
> +state_transition. In such an automaton, cycle advance transitions are
> +available only for these collapsed states. This option is useful for
> +ports that want to use the @code{ndfa} option, but also want to use
> +@code{define_query_cpu_unit} to assign units to insns issued in a cycle.
> +
> +@item
> @dfn{progress} means output of a progress bar showing how many states
> were generated so far for automaton being processed. This is useful
> during debugging a @acronym{DFA} description. If you see too many
> @@ -7984,11 +8134,14 @@
>
> When @code{define_cond_exec} is used, an implicit reference to
> the @code{predicable} instruction attribute is made.
> -@xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
> -exactly two elements in its @var{list-of-values}). Further, it must
> -not be used with complex expressions. That is, the default and all
> -uses in the insns must be a simple constant, not dependent on the
> -alternative or anything else.
> +@xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
> +exactly two elements in its @var{list-of-values}), with the possible
> +values being @code{no} and @code{yes}. The default and all uses in
> +the insns must be a simple constant, not a complex expressions. It
> +may, however, depend on the alternative, by using a comma-separated
> +list of values. If that is the case, the port should also define an
> +@code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
> +should also allow only @code{no} and @code{yes} as its values.
>
> For each @code{define_insn} for which the @code{predicable}
> attribute is true, a new @code{define_insn} pattern will be
--
Yao Qi <qiyaoltc AT gmail DOT com>
You are wise, witty, and wonderful, but you spend too much time reading
this sort of trash.
Index: md.texi
===================================================================
--- md.texi (revision 374)
+++ md.texi (working copy)
@@ -2640,67 +2640,6 @@
一个内存地址，基于Y或者Z指针，加上一个位移
@end table
-@en @item CRX Architecture---@file{config/crx/crx.h}
-@en @table @code
-@en
-@en @item b
-@en Registers from r0 to r14 (registers without stack pointer)
-@en
-@en @item l
-@en Register r16 (64-bit accumulator lo register)
-@en
-@en @item h
-@en Register r17 (64-bit accumulator hi register)
-@en
-@en @item k
-@en Register pair r16-r17. (64-bit accumulator lo-hi pair)
-@en
-@en @item I
-@en Constant that fits in 3 bits
-@en
-@en @item J
-@en Constant that fits in 4 bits
-@en
-@en @item K
-@en Constant that fits in 5 bits
-@en
-@en @item L
-@en Constant that is one of @minus{}1, 4, @minus{}4, 7, 8, 12, 16, 20, 32, 48
-@en
-@en @item G
-@en Floating point constant that is legal for store immediate
-@en @end table
-@item CRX Architecture---@file{config/crx/crx.h}
-@table @code
-
-@item b
-寄存器从r0到r14（不含栈指针）
-
-@item l
-寄存器r16（64位累加器lo寄存器）
-
-@item h
-寄存器r17（64位累加器hi寄存器）
-
-@item k
-寄存器对r16-r17（64位累加器lo-hi寄存器对）
-
-@item I
-3位的常量
-
-@item J
-4位的常量
-
-@item K
-5位的常量
-
-@item L
-常量-1, 4, -4, 7, 8, 12, 16, 20, 32, 48
-
-@item G
-浮点常量，合法的可以用于存储的立即数。
-@end table
-
@en @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
@en @table @code
@en @item a
@@ -4343,81 +4282,6 @@
允许在clr中使用的非寄存器操作数
@end table
-@item Motorola 68HC11 & 68HC12 families---@file{config/m68hc11/m68hc11.h}
-@table @code
-@item a
-@en Register `a'
-寄存器`a'
-
-@item b
-@en Register `b'
-寄存器`b'
-
-@item d
-@en Register `d'
-寄存器`d'
-
-@item q
-@en An 8-bit register
-8位寄存器
-
-@item t
-@en Temporary soft register _.tmp
-临时软寄存器_.tmp
-
-@item u
-@en A soft register _.d1 to _.d31
-软寄存器_.d1 到 _.d31
-
-@item w
-@en Stack pointer register
-栈指针寄存器
-
-@item x
-@en Register `x'
-寄存器`x'
-
-@item y
-@en Register `y'
-寄存器`y'
-
-@item z
-@en Pseudo register `z' (replaced by `x' or `y' at the end)
-伪寄存器`z' (在后来被`x' 或 `y'替换)
-
-@item A
-@en An address register: x, y or z
-地址寄存器：x, y 或 z
-
-@item B
-@en An address register: x or y
-地址寄存器：x 或 y
-
-@item D
-@en Register pair (x:d) to form a 32-bit value
-寄存器(x:d)，形成一个32位的值
-
-@item L
-@en Constants in the range @minus{}65536 to 65535
-常量，范围在@minus{}65536 到 65535
-
-@item M
-@en Constants whose 16-bit low part is zero
-常量，低16位为零
-
-@item N
-@en Constant integer 1 or @minus{}1
-常整数1 或 @minus{}1
-
-@item O
-@en Constant integer 16
-常整数16
-
-@item P
-@en Constants in the range @minus{}8 to 2
-常量，范围在@minus{}8 到 2
-@end table
-
@item Moxie---@file{config/moxie/constraints.md}
@table @code
@item A
@@ -5182,6 +5046,89 @@
@end table
++@item TI C6X family---@file{config/c6x/constraints.md}
+@table @code
+@item a
+Register file A (A0--A31).
+
+@item b
+Register file B (B0--B31).
+
+@item A
+Predicate registers in register file A (A0--A2 on C64X and
+higher, A1 and A2 otherwise).
+
+@item B
+Predicate registers in register file B (B0--B2).
+
+@item C
+A call-used register in register file B (B0--B9, B16--B31).
+
+@item Da
+Register file A, excluding predicate registers (A3--A31,
+plus A0 if not C64X or higher).
+
+@item Db
+Register file B, excluding predicate registers (B3--B31).
+
+@item Iu4
+Integer constant in the range 0 @dots{} 15.
+
+@item Iu5
+Integer constant in the range 0 @dots{} 31.
+
+@item In5
+Integer constant in the range @minus{}31 @dots{} 0.
+
+@item Is5
+Integer constant in the range @minus{}16 @dots{} 15.
+
+@item I5x
+Integer constant that can be the operand of an ADDA or a SUBA insn.
+
+@item IuB
+Integer constant in the range 0 @dots{} 65535.
+
+@item IsB
+Integer constant in the range @minus{}32768 @dots{} 32767.
+
+@item IsC
+Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
+
+@item Jc
+Integer constant that is a valid mask for the clr instruction.
+
+@item Js
+Integer constant that is a valid mask for the set instruction.
+
+@item Q
+Memory location with A base register.
+
+@item R
+Memory location with B base register.
+
+@ifset INTERNALS
+@item S0
+On C64x+ targets, a GP-relative small data reference.
+
+@item S1
+Any kind of @code{SYMBOL_REF}, for use in a call address.
+
+@item Si
+Any kind of immediate operand, unless it matches the S0 constraint.
+
+@item T
+Memory location with B base register, but not using a long offset.
+
+@item W
+A memory operand with an address that can't be used in an unaligned access.
+
+@end ifset
+@item Z
+Register B14 (aka DP).
+
+@end table
+
@en @item Xtensa---@file{config/xtensa/constraints.md}
@en @table @code
@en @item a
@@ -5979,9 +5926,51 @@
@en into consecutive memory locations. Operand 0 is the first of the
@en consecutive memory locations, operand 1 is the first register, and
@en operand 2 is a constant: the number of consecutive registers.
+类似于@samp{load_multiple}，不过是将多个连续的寄存器存储到连续的内存位置。操作数0为连续内存位置的第一个，操作数1为第一个寄存器，操作数2为常量：连续寄存器的数目。
+@cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
+@item @samp{vec_load_lanes@var{m}@var{n}}
+Perform an interleaved load of several vectors from memory operand 1
+into register operand 0. Both operands have mode @var{m}. The register
+operand is viewed as holding consecutive vectors of mode @var{n},
+while the memory operand is a flat array that contains the same number
+of elements. The operation is equivalent to:
+
+@smallexample
+int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
+for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
+ for (i = 0; i < c; i++)
+ operand0[i][j] = operand1[j * c + i];
+@end smallexample
+
+For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
+from memory into a register of mode @samp{TI}@. The register
+contains two consecutive vectors of mode @samp{V4HI}@.
+
+This pattern can only be used if:
+@smallexample
+TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
+@end smallexample
+is true. GCC assumes that, if a target supports this kind of
+instruction for some mode @var{n}, it also supports unaligned
+loads for vectors of mode @var{n}.
+
+@cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
+@item @samp{vec_store_lanes@var{m}@var{n}}
+Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
+and register operands reversed. That is, the instruction is
+equivalent to:
+
+@smallexample
+int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
+for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
+ for (i = 0; i < c; i++)
+ operand0[j * c + i] = operand1[i][j];
+@end smallexample
+
+for a memory operand 0 and register operand 1.
+
@cindex @samp{store_multiple} instruction pattern
@item @samp{store_multiple}
-类似于@samp{load_multiple}，不过是将多个连续的寄存器存储到连续的内存位置。操作数0为连续内存位置的第一个，操作数1为第一个寄存器，操作数2为常量：连续寄存器的数目。
@en @cindex @code{vec_set@var{m}} instruction pattern
@en @item @samp{vec_set@var{m}}
@@ -6035,6 +6024,17 @@
@en and operand 1 is parallel containing values for individual fields.
将向量初始化为给定的值。操作数0为要初始化的向量，操作数1并行的包含每个域的值。
+@cindex @code{vcond@var{m}@var{n}} instruction pattern
+@item @samp{vcond@var{m}@var{n}}
+Output a conditional vector move. Operand 0 is the destination to
+receive a combination of operand 1 and operand 2, which are of mode @var{m},
+dependent on the outcome of the predicate in operand 3 which is a
+vector comparison with operands of mode @var{n} in operands 4 and 5. The
+modes @var{m} and @var{n} should have the same size. Operand 0
+will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
+where @var{msk} is computed by element-wise evaluation of the vector
+comparison with a truth value of all-ones and a false value of all-zeros.
+
@cindex @code{push@var{m}1} instruction pattern
@item @samp{push@var{m}1}
@en Output a push instruction. Operand 0 is value to push. Used only when
@@ -6964,8 +6964,14 @@
@en that may access an invalid page or segment and cause a fault. The
@en effect of the instruction is to store a value in operand 0 whose sign
@en indicates the result of the comparison.
-字符串比较指令，有5个操作数。操作数0为输出，机器模式为@var{m}。剩下的4个操作数类似于@samp{movmem@var{m}}的操作数。两个指定的内存块按字节来进行比较，按照字典顺序，从每个字符串的起始处开始。指令不允许一次取多个字节，因为每个字符串都可能在第一个字节中终止，读取后面的字节可能会访问一个无效的页或者段，并产生一个缺失。该指令的效果是将值存放在操作数0中，其符号表示了比较的结果。
-
+
+字符串比较指令，有5个操作数。操作数0为输出，机器模式为@var{m}。剩下的4个操作数类似于@samp{movmem@var{m}}的操作数。两个指定的内存块按字节来进行比较，按照字典顺序，从每个字符串的起始处开始。指令不允许一次取多个字节，因为每个字符串都可能在第一个字节中终止，读取后面的字节可能会访问一个无效的页或者段，并产生一个缺失。
+@c 该指令的效果是将值存放在操作数0中，其符号表示了比较的结果。
+The
+comparison terminates early if the fetched bytes are different or if
+they are equal to zero. The effect of the instruction is to store a
+value in operand 0 whose sign indicates the result of the comparison.
+
@cindex @code{cmpstr@var{m}} instruction pattern
@item @samp{cmpstr@var{m}}
@en String compare instruction, without known maximum length. Operand 0 is the
@@ -6986,8 +6992,13 @@
@en first byte and reading past that may access an invalid page or segment and
@en cause a fault. The effect of the instruction is to store a value in
operand 0
@en whose sign indicates the result of the comparison.
-两个指定的内存块按字节来进行比较，按照字典顺序，从每个字符串的起始处开始。指令不允许一次取多个字节，因为每个字符串都可能在第一个字节中终止，读取后面的字节可能会访问一个无效的页或者段，并产生一个缺失。该指令的效果是将值存放在操作数0中，其符号表示了比较的结果。
-
+两个指定的内存块按字节来进行比较，按照字典顺序，从每个字符串的起始处开始。指令不允许一次取多个字节，因为每个字符串都可能在第一个字节中终止，读取后面的字节可能会访问一个无效的页或者段，并产生一个缺失。
+@c 该指令的效果是将值存放在操作数0中，其符号表示了比较的结果。
+The comparison will terminate when the fetched bytes
+are different or if they are equal to zero. The effect of the
+instruction is to store a value in operand 0 whose sign indicates the
+result of the comparison.
+
@cindex @code{cmpmem@var{m}} instruction pattern
@item @samp{cmpmem@var{m}}
@en Block compare instruction, with five operands like the operands
@@ -6997,7 +7008,12 @@
@en any bytes in the two memory blocks. The effect of the instruction is
@en to store a value in operand 0 whose sign indicates the result of the
@en comparison.
-块比较指令，这5个操作数类似于@samp{cmpstr@var{m}}。两个指定的内存块按字节来进行比较，按照字典顺序，从每个字符串的起始处开始。不像@samp{cmpstr@var{m}}，该指令可以在两个内存块中取任意个字节。该指令的效果是将值存放在操作数0中，其符号表示了比较的结果。
+块比较指令，这5个操作数类似于@samp{cmpstr@var{m}}。两个指定的内存块按字节来进行比较，按照字典顺序，从每个字符串的起始处开始。不像@samp{cmpstr@var{m}}，该指令可以在两个内存块中取任意个字节。
+@c 该指令的效果是将值存放在操作数0中，其符号表示了比较的结果。
+Also unlike @samp{cmpstr@var{m}}
+the comparison will not stop if both bytes are zero. The effect of
+the instruction is to store a value in operand 0 whose sign indicates
+the result of the comparison.
@en @cindex @code{strlen@var{m}} instruction pattern
@en @item @samp{strlen@var{m}}
@@ -7368,6 +7384,20 @@
类似@samp{mov@var{m}}指令模式，该指令模式也在RTL生成阶段之后被使用。这种情况下，其用来支持一些机器，从函数中返回通常需要多个指令，但是某些类别的函数只需要一条指令来实现返回。通常，可以适用的函数为那些不需要保存任何寄存器或者分配栈空间的函数。
+It is valid for this pattern to expand to an instruction using
+@code{simple_return} if no epilogue is required.
+
+@cindex @code{simple_return} instruction pattern
+@item @samp{simple_return}
+Subroutine return instruction. This instruction pattern name should be
+defined only if a single instruction can do all the work of returning
+from a function on a path where no epilogue is required. This pattern
+is very similar to the @code{return} instruction pattern, but it is emitted
+only by the shrink-wrapping optimization on paths where the function
+prologue has not been executed, and a function return should occur without
+any of the effects of the epilogue. Additional uses may be introduced on
+paths where both the prologue and the epilogue have executed.
+
@en @findex reload_completed
@en @findex leaf_function_p
@en For such machines, the condition specified in this pattern should only
@@ -7886,6 +7916,14 @@
@code{prologue}指令模式对于执行指令调度的目标机尤其有用。
+@en @cindex @code{window_save} instruction pattern
+@en @anchor{window_save instruction pattern}
+@item @samp{window_save}
+This pattern, if defined, emits RTL for a register window save. It should
+be defined if the target machine has register windows but the window events
+are decoupled from calls to subroutines. The canonical example is the SPARC
+architecture.
+
@cindex @code{epilogue} instruction pattern
@anchor{epilogue instruction pattern}
@item @samp{epilogue}
@@ -8202,7 +8240,7 @@
@en @cindex @code{stack_protect_set} instruction pattern
@en @item @samp{stack_protect_set}
@en
-@en This pattern, if defined, moves a @code{Pmode} value from the memory
+@en This pattern, if defined, moves a @code{ptr_mode} value from the memory
@en in operand 1 to the memory in operand 0 without leaving the value in
@en a register afterward. This is to avoid leaking the value some place
@en that an attacker might use to rewrite the stack guard slot after
@@ -8869,6 +8907,21 @@
@en will be written using @code{zero_extract} rather than the equivalent
@en @code{and} or @code{sign_extract} operations.
@en
+@en @cindex @code{mult}, canonicalization of
+@en @item
+@en @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
+@en (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
+@en (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and
likewise
+@en for @code{zero_extend}.
+@en @item
+@en @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
+@en @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
+@en to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
+@en @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
+@en patterns using @code{zero_extend} and @code{lshiftrt}. If the second
+@en operand of @code{mult} is also a shift, then that is extended also.
+@en This transformation is only applied when it can be proven that the
+@en original operation had sufficient precision to prevent overflow.
@en @end itemize
@en
@en Further canonicalization rules are defined in the function
@@ -10254,6 +10307,14 @@
@en information on the handling of defaults. @xref{Constant Attributes},
@en for information on attributes that do not depend on any particular insn.
@var{name} 为一个字符串，指定了被定义的属性名。
+Some attributes are used in a special way by the rest of the compiler. The
+@code{enabled} attribute can be used to conditionally enable or disable
+insn alternatives (@pxref{Disable Insn Alternatives}). The @code{predicable}
+attribute, together with a suitable @code{define_cond_exec}
+(@pxref{Conditional Execution}), can be used to automatically generate
+conditional variants of instruction patterns. The compiler internally uses
+the names @code{ce_enabled} and @code{nonce_enabled}, so they should not be
+used elsewhere as alternative names.
@var{list-of-values} 或者为一个字符串，指定了可以赋予属性的逗号分隔
的值的列表，或者为一个空字符串，表示属性接受一个数字值。
@@ -10516,6 +10577,31 @@
@var{constraints}操作数被忽略并且应该为空字符串。
+@cindex @code{match_test} and attributes
+@item (match_test @var{c-expr})
+The test is true if C expression @var{c-expr} is true. In non-constant
+attributes, @var{c-expr} has access to the following variables:
+
+@table @var
+@item insn
+The rtl instruction under test.
+@item which_alternative
+The @code{define_insn} alternative that @var{insn} matches.
+@xref{Output Statement}.
+@item operands
+An array of @var{insn}'s rtl operands.
+@end table
+
+@var{c-expr} behaves like the condition in a C @code{if} statement,
+so there is no need to explicitly convert the expression into a boolean
+0 or 1 value. For example, the following two tests are equivalent:
+
+@smallexample
+(match_test "x & 2")
+(match_test "(x & 2) != 0")
+@end smallexample
+
+
@en @cindex @code{le} and attributes
@en @cindex @code{leu} and attributes
@en @cindex @code{lt} and attributes
@@ -11705,7 +11791,17 @@
@en the string are separated by commas.
@var{number}定义了给定字符串@var{out_insn_names}的指令所产生的结果，
什么时候可以由给定字符串@var{in_insn_names}的指令使用。
-字符串中的指令由逗号分隔。
+@c 字符串中的指令由逗号分隔。
+Each of these
+strings is a comma-separated list of filename-style globs and
+they refer to the names of @code{define_insn_reservation}s.
+For example:
+@smallexample
+(define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
+@end smallexample
+defines a bypass between instructions that start with
+@samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
+@samp{cpu1_load_}.
@en @var{guard} is an optional string giving the name of a C function which
@en defines an additional guard for the bypass. The function will get the
@@ -11912,6 +12008,12 @@
@en @dfn{w} means a generation of warning instead of error for
@en non-critical errors.
@en
+ @item
+@en @dfn{no-comb-vect} prevents the automaton generator from generating
+@en two data structures and comparing them for space efficiency. Using
+@en a comb vector to represent transitions may be better, but it can be
+@en very expensive to construct. This option is useful if the build
+@en process spends an unacceptably long time in genautomata.
@en @item
@en @dfn{ndfa} makes nondeterministic finite state automata. This affects
@en the treatment of operator @samp{|} in the regular expressions. The
@@ -11921,6 +12023,15 @@
@en may be rejected by reservations in the subsequent insns.
@en
@en @item
+@en @dfn{collapse-ndfa} modifies the behaviour of the generator when
+@en producing an automaton. An additional state transition to collapse a
+@en nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
+@en state is generated. It can be triggered by passing @code{const0_rtx} to
+@en state_transition. In such an automaton, cycle advance transitions are
+@en available only for these collapsed states. This option is useful for
+@en ports that want to use the @code{ndfa} option, but also want to use
+@en @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
+@en @item
@en @dfn{progress} means output of a progress bar showing how many states
@en were generated so far for automaton being processed. This is useful
@en during debugging a @acronym{DFA} description. If you see too many
@@ -12107,11 +12218,14 @@
@en
@en When @code{define_cond_exec} is used, an implicit reference to
@en the @code{predicable} instruction attribute is made.
-@en @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
-@en exactly two elements in its @var{list-of-values}). Further, it must
-@en not be used with complex expressions. That is, the default and all
-@en uses in the insns must be a simple constant, not dependent on the
-@en alternative or anything else.
+@en @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
+@en exactly two elements in its @var{list-of-values}), with the possible
+@en values being @code{no} and @code{yes}. The default and all uses in
+@en the insns must be a simple constant, not a complex expressions. It
+@en may, however, depend on the alternative, by using a comma-separated
+@en list of values. If that is the case, the port should also define an
+@en @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
+@en should also allow only @code{no} and @code{yes} as its values.
@en
@en For each @code{define_insn} for which the @code{predicable}
@en attribute is true, a new @code{define_insn} pattern will be
@@ -12124,11 +12238,21 @@
处理通用的情况，有一个全局变量 @code{current_insn_predicate}，在当前
insn被predicate时其将包含整个predicate，否则将为 @code{NULL}。
-当使用 @code{define_cond_exec} 时，将会创建一个对 @code{predicable} 指
-令属性的隐式引用。@pxref{Insn Attributes}。该属性并须为布尔的（即在它的
-@var{list-of-values} 中具有确切的两个元素）。甚至，其必须不能使用复杂
-表达式。也就是，insn中的缺省的和所有的使用都必须为一个简单常量，不能依
-赖于可选项或其它。
+@c 当使用 @code{define_cond_exec} 时，将会创建一个对 @code{predicable} 指
+@c 令属性的隐式引用。@pxref{Insn Attributes}。该属性并须为布尔的（即在它的
+@c @var{list-of-values} 中具有确切的两个元素）。甚至，其必须不能使用复杂
+@c 表达式。也就是，insn中的缺省的和所有的使用都必须为一个简单常量，不能依
+@c 赖于可选项或其它。
+ When @code{define_cond_exec} is used, an implicit reference to
+ the @code{predicable} instruction attribute is made.
+@xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
+exactly two elements in its @var{list-of-values}), with the possible
+values being @code{no} and @code{yes}. The default and all uses in
+the insns must be a simple constant, not a complex expressions. It
+may, however, depend on the alternative, by using a comma-separated
+list of values. If that is the case, the port should also define an
+@code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
+should also allow only @code{no} and @code{yes} as its values.
对于每个 @code{predicable} 属性为真的 @code{define_insn}，一个新的匹配
一个指令predicate版本的 @code{define_insn} 指令模式将被生成。例如，
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