[haiku-commits] r33715 - in haiku/vendor/freebsd/current/dev: mii msk
- From: pulkomandy@xxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Wed, 21 Oct 2009 22:31:33 +0200 (CEST)
Author: pulkomandy
Date: 2009-10-21 22:31:33 +0200 (Wed, 21 Oct 2009)
New Revision: 33715
Changeset: http://dev.haiku-os.org/changeset/33715/haiku
Modified:
haiku/vendor/freebsd/current/dev/mii/brgphyreg.h
haiku/vendor/freebsd/current/dev/mii/e1000phy.c
haiku/vendor/freebsd/current/dev/mii/e1000phyreg.h
haiku/vendor/freebsd/current/dev/msk/if_msk.c
haiku/vendor/freebsd/current/dev/msk/if_mskreg.h
Log:
Updated msk and related mii to freebsd current.
Modified: haiku/vendor/freebsd/current/dev/mii/brgphyreg.h
===================================================================
--- haiku/vendor/freebsd/current/dev/mii/brgphyreg.h 2009-10-21 20:26:40 UTC
(rev 33714)
+++ haiku/vendor/freebsd/current/dev/mii/brgphyreg.h 2009-10-21 20:31:33 UTC
(rev 33715)
@@ -29,7 +29,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD: src/sys/dev/mii/brgphyreg.h,v 1.11 2008/04/29 19:47:13 jhb Exp $
+ * $FreeBSD$
*/
#ifndef _DEV_MII_BRGPHYREG_H_
@@ -262,103 +262,103 @@
#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */
#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */
-/*******************************************************/
-/* Begin: Shared SerDes PHY register definitions */
-/*******************************************************/
-
-/* SerDes autoneg is different from copper */
-#define BRGPHY_SERDES_ANAR 0x04
-#define BRGPHY_SERDES_ANAR_FDX 0x0020
-#define BRGPHY_SERDES_ANAR_HDX 0x0040
-#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7)
-#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7)
-#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7)
-#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7)
-
-#define BRGPHY_SERDES_ANLPAR 0x05
-#define BRGPHY_SERDES_ANLPAR_FDX 0x0020
-#define BRGPHY_SERDES_ANLPAR_HDX 0x0040
-#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7)
-#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7)
-#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7)
-#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7)
-
-/*******************************************************/
-/* End: Shared SerDes PHY register definitions */
-/*******************************************************/
-
-/*******************************************************/
-/* Begin: PHY register values for the 5706 PHY */
-/*******************************************************/
-
-/*
- * Shadow register 0x1C, bit 15 is write enable,
- * bits 14-10 select function (0x00 to 0x1F).
- */
-#define BRGPHY_MII_SHADOW_1C 0x1C
+/*******************************************************/
+/* Begin: Shared SerDes PHY register definitions */
+/*******************************************************/
+
+/* SerDes autoneg is different from copper */
+#define BRGPHY_SERDES_ANAR 0x04
+#define BRGPHY_SERDES_ANAR_FDX 0x0020
+#define BRGPHY_SERDES_ANAR_HDX 0x0040
+#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7)
+#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7)
+#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7)
+#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7)
+
+#define BRGPHY_SERDES_ANLPAR 0x05
+#define BRGPHY_SERDES_ANLPAR_FDX 0x0020
+#define BRGPHY_SERDES_ANLPAR_HDX 0x0040
+#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7)
+#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7)
+#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7)
+#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7)
+
+/*******************************************************/
+/* End: Shared SerDes PHY register definitions */
+/*******************************************************/
+
+/*******************************************************/
+/* Begin: PHY register values for the 5706 PHY */
+/*******************************************************/
+
+/*
+ * Shadow register 0x1C, bit 15 is write enable,
+ * bits 14-10 select function (0x00 to 0x1F).
+ */
+#define BRGPHY_MII_SHADOW_1C 0x1C
#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000
#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00
-
+
/* Shadow 0x1C Mode Control Register (select value 0x1F) */
#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)
/* When set, Regs 0-0x0F are 1000X, else 1000T */
-#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001
+#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001
#define BRGPHY_MII_TEST1 0x1E
#define BRGPHY_TEST1_TRIM_EN 0x0010
#define BRGPHY_TEST1_CRC_EN 0x8000
#define BRGPHY_MII_TEST2 0x1F
-
-/*******************************************************/
-/* End: PHY register values for the 5706 PHY */
-/*******************************************************/
-
-/*******************************************************/
-/* Begin: PHY register values for the 5708S SerDes PHY */
-/*******************************************************/
-
-/* Autoneg Next Page Transmit 1 Regiser */
-#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B
-#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001
-
-/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */
-#define BRGPHY_5708S_BLOCK_ADDR 0x1f
+
+/*******************************************************/
+/* End: PHY register values for the 5706 PHY */
+/*******************************************************/
+
+/*******************************************************/
+/* Begin: PHY register values for the 5708S SerDes PHY */
+/*******************************************************/
+
+/* Autoneg Next Page Transmit 1 Regiser */
+#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B
+#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001
+
+/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */
+#define BRGPHY_5708S_BLOCK_ADDR 0x1f
#define BRGPHY_5708S_DIG_PG0 0x0000
#define BRGPHY_5708S_DIG3_PG2 0x0002
#define BRGPHY_5708S_TX_MISC_PG5 0x0005
-
-/* 5708S SerDes "Digital" Registers (page 0) */
-#define BRGPHY_5708S_PG0_1000X_CTL1 0x10
-#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010
-#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001
-
-#define BRGPHY_5708S_PG0_1000X_STAT1 0x14
-#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002
-#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3)
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3)
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3)
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3)
-
-
-#define BRGPHY_5708S_PG0_1000X_CTL2 0x11
-#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001
-
-/* 5708S SerDes "Digital 3" Registers (page 2) */
-#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10
-#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001
-
-/* 5708S SerDes "TX Misc" Registers (page 5) */
-#define BRGPHY_5708S_PG5_2500STATUS1 0x10
-#define BRGPHY_5708S_PG5_TXACTL1 0x15
-#define BRGPHY_5708S_PG5_TXACTL3 0x17
-/*******************************************************/
-/* End: PHY register values for the 5708S SerDes PHY */
-/*******************************************************/
-
+/* 5708S SerDes "Digital" Registers (page 0) */
+#define BRGPHY_5708S_PG0_1000X_CTL1 0x10
+#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010
+#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001
+
+#define BRGPHY_5708S_PG0_1000X_STAT1 0x14
+#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002
+#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3)
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3)
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3)
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3)
+
+
+#define BRGPHY_5708S_PG0_1000X_CTL2 0x11
+#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001
+
+/* 5708S SerDes "Digital 3" Registers (page 2) */
+#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10
+#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001
+
+/* 5708S SerDes "TX Misc" Registers (page 5) */
+#define BRGPHY_5708S_PG5_2500STATUS1 0x10
+#define BRGPHY_5708S_PG5_TXACTL1 0x15
+#define BRGPHY_5708S_PG5_TXACTL3 0x17
+
+/*******************************************************/
+/* End: PHY register values for the 5708S SerDes PHY */
+/*******************************************************/
+
#define BRGPHY_INTRS \
~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG)
Modified: haiku/vendor/freebsd/current/dev/mii/e1000phy.c
===================================================================
--- haiku/vendor/freebsd/current/dev/mii/e1000phy.c 2009-10-21 20:26:40 UTC
(rev 33714)
+++ haiku/vendor/freebsd/current/dev/mii/e1000phy.c 2009-10-21 20:31:33 UTC
(rev 33715)
@@ -59,6 +59,9 @@
#include "miidevs.h"
#include <dev/mii/e1000phyreg.h>
+/* XXX */
+#include <machine/bus.h>
+#include <dev/msk/if_mskreg.h>
#include "miibus_if.h"
@@ -68,6 +71,7 @@
struct e1000phy_softc {
struct mii_softc mii_sc;
int mii_model;
+ struct msk_mii_data *mmd;
};
static device_method_t e1000phy_methods[] = {
@@ -130,6 +134,7 @@
struct mii_softc *sc;
struct mii_attach_args *ma;
struct mii_data *mii;
+ struct ifnet *ifp;
esc = device_get_softc(dev);
sc = &esc->mii_sc;
@@ -145,6 +150,16 @@
mii->mii_instance++;
esc->mii_model = MII_MODEL(ma->mii_id2);
+ ifp = sc->mii_pdata->mii_ifp;
+ if (strcmp(ifp->if_dname, "msk") == 0) {
+ /* XXX */
+ esc->mmd = device_get_ivars(
+ device_get_parent(device_get_parent(dev)));
+ if (esc->mmd != NULL &&
+ (esc->mmd->mii_flags & MIIF_HAVEFIBER) != 0)
+ sc->mii_flags |= MIIF_HAVEFIBER;
+ }
+
switch (esc->mii_model) {
case MII_MODEL_MARVELL_E1011:
case MII_MODEL_MARVELL_E1112:
@@ -199,6 +214,13 @@
reg &= ~E1000_SCR_MODE_MASK;
reg |= E1000_SCR_MODE_1000BX;
PHY_WRITE(sc, E1000_SCR, reg);
+ if (esc->mmd != NULL && esc->mmd->pmd == 'P') {
+ /* Set SIGDET polarity low for SFP module. */
+ PHY_WRITE(sc, E1000_EADR, 1);
+ reg = PHY_READ(sc, E1000_SCR);
+ reg |= E1000_SCR_FIB_SIGDET_POLARITY;
+ PHY_WRITE(sc, E1000_SCR, reg);
+ }
PHY_WRITE(sc, E1000_EADR, page);
}
} else {
@@ -240,17 +262,15 @@
if (esc->mii_model == MII_MODEL_MARVELL_E1116 ||
esc->mii_model == MII_MODEL_MARVELL_E1149) {
- page = PHY_READ(sc, E1000_EADR);
- /* Select page 2, MAC specific control register. */
PHY_WRITE(sc, E1000_EADR, 2);
reg = PHY_READ(sc, E1000_SCR);
reg |= E1000_SCR_RGMII_POWER_UP;
PHY_WRITE(sc, E1000_SCR, reg);
- PHY_WRITE(sc, E1000_EADR, page);
+ PHY_WRITE(sc, E1000_EADR, 0);
}
}
- switch (MII_MODEL(esc->mii_model)) {
+ switch (esc->mii_model) {
case MII_MODEL_MARVELL_E3082:
case MII_MODEL_MARVELL_E1112:
case MII_MODEL_MARVELL_E1118:
@@ -487,8 +507,11 @@
return;
}
} else {
- if (ssr & E1000_SSR_1000MBS)
- mii->mii_media_active |= IFM_1000_SX;
+ /*
+ * Some fiber PHY(88E1112) does not seem to set resolved
+ * speed so always assume we've got IFM_1000_SX.
+ */
+ mii->mii_media_active |= IFM_1000_SX;
}
if (ssr & E1000_SSR_DUPLEX)
Modified: haiku/vendor/freebsd/current/dev/mii/e1000phyreg.h
===================================================================
--- haiku/vendor/freebsd/current/dev/mii/e1000phyreg.h 2009-10-21 20:26:40 UTC
(rev 33714)
+++ haiku/vendor/freebsd/current/dev/mii/e1000phyreg.h 2009-10-21 20:31:33 UTC
(rev 33715)
@@ -248,6 +248,11 @@
#define E1000_SCR_EN_DETECT_MASK 0x0300
+/* 88E1112 page 1 fiber specific control */
+#define E1000_SCR_FIB_TX_DIS 0x0008
+#define E1000_SCR_FIB_SIGDET_POLARITY 0x0200
+#define E1000_SCR_FIB_FORCE_LINK 0x0400
+
/* 88E1112 page 2 */
#define E1000_SCR_MODE_MASK 0x0380
#define E1000_SCR_MODE_AUTO 0x0180
Modified: haiku/vendor/freebsd/current/dev/msk/if_msk.c
===================================================================
--- haiku/vendor/freebsd/current/dev/msk/if_msk.c 2009-10-21 20:26:40 UTC
(rev 33714)
+++ haiku/vendor/freebsd/current/dev/msk/if_msk.c 2009-10-21 20:31:33 UTC
(rev 33715)
@@ -223,6 +223,8 @@
"Marvell Yukon 88E8072 Gigabit Ethernet" },
{ VENDORID_DLINK, DEVICEID_DLINK_DGE550SX,
"D-Link 550SX Gigabit Ethernet" },
+ { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX,
+ "D-Link 560SX Gigabit Ethernet" },
{ VENDORID_DLINK, DEVICEID_DLINK_DGE560T,
"D-Link 560T Gigabit Ethernet" }
};
@@ -601,7 +603,7 @@
mchash[1] = 0xffff;
} else {
mode |= GM_RXCR_UCF_ENA;
- IF_ADDR_LOCK(ifp);
+ if_maddr_rlock(ifp);
TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
if (ifma->ifma_addr->sa_family != AF_LINK)
continue;
@@ -612,7 +614,7 @@
/* Set the corresponding bit in the hash table. */
mchash[crc >> 5] |= 1 << (crc & 0x1f);
}
- IF_ADDR_UNLOCK(ifp);
+ if_maddr_runlock(ifp);
if (mchash[0] != 0 || mchash[1] != 0)
mode |= GM_RXCR_MCF_ENA;
}
@@ -1445,6 +1447,7 @@
struct msk_softc *sc;
struct msk_if_softc *sc_if;
struct ifnet *ifp;
+ struct msk_mii_data *mmd;
int i, port, error;
uint8_t eaddr[6];
@@ -1454,7 +1457,8 @@
error = 0;
sc_if = device_get_softc(dev);
sc = device_get_softc(device_get_parent(dev));
- port = *(int *)device_get_ivars(dev);
+ mmd = device_get_ivars(dev);
+ port = mmd->port;
sc_if->msk_if_dev = dev;
sc_if->msk_port = port;
@@ -1600,7 +1604,8 @@
mskc_attach(device_t dev)
{
struct msk_softc *sc;
- int error, msic, msir, *port, reg;
+ struct msk_mii_data *mmd;
+ int error, msic, msir, reg;
sc = device_get_softc(dev);
sc->msk_dev = dev;
@@ -1669,10 +1674,6 @@
CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
- if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
- sc->msk_coppertype = 0;
- else
- sc->msk_coppertype = 1;
/* Check number of MACs. */
sc->msk_num_port = 1;
if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
@@ -1812,15 +1813,18 @@
error = ENXIO;
goto fail;
}
- port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
- if (port == NULL) {
+ mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO);
+ if (mmd == NULL) {
device_printf(dev, "failed to allocate memory for "
"ivars of PORT_A\n");
error = ENXIO;
goto fail;
}
- *port = MSK_PORT_A;
- device_set_ivars(sc->msk_devs[MSK_PORT_A], port);
+ mmd->port = MSK_PORT_A;
+ mmd->pmd = sc->msk_pmd;
+ if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P')
+ mmd->mii_flags |= MIIF_HAVEFIBER;
+ device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd);
if (sc->msk_num_port > 1) {
sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1);
@@ -1829,15 +1833,18 @@
error = ENXIO;
goto fail;
}
- port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
- if (port == NULL) {
+ mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK |
M_ZERO);
+ if (mmd == NULL) {
device_printf(dev, "failed to allocate memory for "
"ivars of PORT_B\n");
error = ENXIO;
goto fail;
}
- *port = MSK_PORT_B;
- device_set_ivars(sc->msk_devs[MSK_PORT_B], port);
+ mmd->port = MSK_PORT_B;
+ mmd->pmd = sc->msk_pmd;
+ if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd ==
'P')
+ mmd->mii_flags |= MIIF_HAVEFIBER;
+ device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd);
}
error = bus_generic_attach(dev);
@@ -3794,9 +3801,14 @@
/* Set receive filter. */
msk_rxfilter(sc_if);
- /* Flush Rx MAC FIFO on any flow control or error. */
- CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
- GMR_FS_ANY_ERR);
+ if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
+ /* Clear flush mask - HW bug. */
+ CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0);
+ } else {
+ /* Flush Rx MAC FIFO on any flow control or error. */
+ CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
+ GMR_FS_ANY_ERR);
+ }
/*
* Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word
@@ -4188,7 +4200,7 @@
gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
/* Read all MIB Counters with Clear Mode set. */
- for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i++)
+ for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t))
reg = MSK_READ_MIB32(sc_if->msk_port, i);
/* Clear MIB Clear Counter Mode. */
gmac &= ~GM_PAR_MIB_CLR;
Modified: haiku/vendor/freebsd/current/dev/msk/if_mskreg.h
===================================================================
--- haiku/vendor/freebsd/current/dev/msk/if_mskreg.h 2009-10-21 20:26:40 UTC
(rev 33714)
+++ haiku/vendor/freebsd/current/dev/msk/if_mskreg.h 2009-10-21 20:31:33 UTC
(rev 33715)
@@ -148,6 +148,7 @@
* D-Link gigabit ethernet device ID
*/
#define DEVICEID_DLINK_DGE550SX 0x4001
+#define DEVICEID_DLINK_DGE560SX 0x4002
#define DEVICEID_DLINK_DGE560T 0x4b00
#define BIT_31 (1 << 31)
@@ -2403,6 +2404,12 @@
#define MSK_TX_TIMEOUT 5
#define MSK_PUT_WM 10
+struct msk_mii_data {
+ int port;
+ uint32_t pmd;
+ int mii_flags;
+};
+
/* Forward decl. */
struct msk_if_softc;
@@ -2466,7 +2473,6 @@
uint8_t msk_num_port;
int msk_ramsize; /* amount of SRAM on NIC */
uint32_t msk_pmd; /* physical media type */
- uint32_t msk_coppertype;
uint32_t msk_intrmask;
uint32_t msk_intrhwemask;
uint32_t msk_pflags;
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