Don't know why these folks think that there are so many contractors out there with active clearances, I'm assuming that they will eventually figure it out, and accept non-cleared contractors, or full timers that can get a clearance. Anyway, here it is.................. --- On Mon, 7/19/10, Alex Moreno <alex@xxxxxxxxxxxx> wrote: From: Alex Moreno <alex@xxxxxxxxxxxx> Subject: Triple Crown Consulting-Alex To: john.laverdier@xxxxxxxxx Date: Monday, July 19, 2010, 9:09 PM John, Here is the description for the project in Irvine/Torrance. Thanks for the help. 3-4 spots, 6 month contract, Clearance required. Requires skill in all phases of ASIC design; detailed design requirements, architecture design, VHDL or Verilog RTL detailed design, simulation, synthesis, timing analysis, test vector generation; creating simulation and prototype verification test plans, conduction hardware design demo, participating in design reviews; experienced in requirements definition and architecture to net-list approval and ASIC buy-off; experience with Cryptography; FPGA place and route, timing analysis and test; debug skills. Working knowledge of VHDL language, ARM7, ARM9, RISC processor, USB, network architecture, space radiation harden design, FPGA design tools and flow. Alex Moreno | Triple Crown Consulting, LLC | Technical Recruiter P: 512.623.5784 | Toll Free: 866.901.8880 ext 123| F: 512.233.53411 3805 Research Blvd. Suite 200 Austin, Texas 78750 www.tripleco.com