Just finished another (long overdue) u-boot repository sync. Here's an
"as-is" patch from our repository against the u-boot CVS HEAD. To build...
cvs -d:pserver:anonymous@xxxxxxxxxxxxxxxxxxx:/cvsroot/u-boot login
cvs -d:pserver:anonymous@xxxxxxxxxxxxxxxxxxx:/cvsroot/u-boot -z6 -q \
co -P u-boot
cd u-boot
patch -p1 < ~/some/path/to/u-boot_edb93xx-20060405.patch
make edb93(01|02|07|12|15)_config
makeDrop the resulting u-boot.bin onto your board using Cirrus' download utility. Serial console comes up at 115200. You'll need to set your environment appropriately as well for DHCP/BOOTP/etc. See the u-boot wiki if you need help with this. See include/configs/edb93xx.h for the memory map.
-Cory
-- Cory T. Tusar Embedded Systems Engineer Videon Central, Inc. 2171 Sandy Drive State College, PA 16801 (814) 235-1111 x316 (814) 235-1118 fax
"Debugging is twice as hard as writing the code in the first place.
Therefore, if you write the code as cleverly as possible, you are,
by definition, not smart enough to debug it." --Brian W. Kernighandiff -urP u-boot.orig-20060405/board/edb93xx/config.mk
u-boot.scrubbed-20060405/board/edb93xx/config.mk
--- u-boot.orig-20060405/board/edb93xx/config.mk 1969-12-31
19:00:00.000000000 -0500
+++ u-boot.scrubbed-20060405/board/edb93xx/config.mk 2006-04-05
09:47:47.000000000 -0400
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2002-2003
+# Adam Bezanson, Network Audio Technologies, Inc., <bezanson@xxxxxxxxxxxxxxxx>
+#
+# Cirrus Logic board for Cirrus Logic EP9312 Rev D. (ARM920T) cpu
+#
+#
+#
+##################################################
+# Assumed configuration for EDB9312 revision 2
+# Internal boot
+# SDRAM chip select: /SDCS3
+# SDRAM size: 64 MB
+# Sync Memory Boot
+#
+# We place the stuff close to the SDRAM upper bound
+TEXT_BASE = 0x05f00000
diff -urP u-boot.orig-20060405/board/edb93xx/edb93xx.c
u-boot.scrubbed-20060405/board/edb93xx/edb93xx.c
--- u-boot.orig-20060405/board/edb93xx/edb93xx.c 1969-12-31
19:00:00.000000000 -0500
+++ u-boot.scrubbed-20060405/board/edb93xx/edb93xx.c 2006-04-05
09:47:47.000000000 -0400
@@ -0,0 +1,182 @@
+/* vim: set ts=8 sw=8 noet: */
+/*
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson@xxxxxxxxxxxxxxxx>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ep93xx.h>
+#include <linux/byteorder/swab.h>
+
+#define HAL_WRITE_UINT32( _register_, _value_ ) \
+ (*((volatile unsigned long *)(_register_)) = (_value_))
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * static inline void delay (unsigned long loops)
+ * {
+ * __asm__ volatile ("1:\n"
+ * "subs %0, %1, #1\n"
+ * "bne 1b":"=r" (loops):"0" (loops));
+ * }
+ */
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned long ClkSet1;
+ unsigned long ClkSet2;
+
+
+ //
+ // Set the output of PLL2 to 192Mhz
+ //
+ ClkSet2 = 0x300dc317;
+
+#ifdef CONFIG_EP9301
+ //
+ // Set the output of the PLL to 332Mhz
+ //
+ ClkSet1 = EP9312_CLKSET1_NBYP | 0x00fa5a;
+
+ //
+ // Set the FCLKDIV value to divide by 2 (166Mhz).
+ //
+ ClkSet1 |= (1 << EP9312_CLKSET1_FCLKDIV_SHIFT);
+
+ //
+ // Set the HCLKDIV value to divide by 5 (66Mhz).
+ //
+ ClkSet1 |= (3 << EP9312_CLKSET1_HCLKDIV_SHIFT);
+#else
+ //
+ // Set the output of the PLL to 400Mhz
+ //
+ ClkSet1 = EP9312_CLKSET1_NBYP | 0x00e39e;
+
+ //
+ // Set the FCLK to 400/2 or 200Mhz
+ //
+ ClkSet1 |= (1 << EP9312_CLKSET1_FCLKDIV_SHIFT);
+
+ //
+ // Set the HCLK to 400/4 or 100Mhz
+ //
+ ClkSet1 |= (2 << EP9312_CLKSET1_HCLKDIV_SHIFT);
+#endif // CONFIG_EP9301
+
+ //
+ // Set PCLKDIV so that PCLK = HCLK / 2
+ //
+ ClkSet1 |= (1 << EP9312_CLKSET1_PCLKDIV_SHIFT);
+
+ HAL_WRITE_UINT32(EP9312_CLKSET1, ClkSet1);
+
+ //
+ // Do the five required nops to keep us clean.
+ //
+ __asm ("nop");
+ __asm ("nop");
+ __asm ("nop");
+ __asm ("nop");
+ __asm ("nop");
+
+ //
+ // Write out the value to ClkSet 2
+ //
+ HAL_WRITE_UINT32(EP9312_CLKSET2, ClkSet2);
+
+ //
+ // Go to Async mode
+ //
+ __asm ("mrc p15, 0, r0, c1, c0, 0");
+ __asm ("orr r0, r0, #0xc0000000");
+ __asm ("mcr p15, 0, r0, c1, c0, 0");
+
+ icache_enable();
+
+#ifdef USE_920T_MMU
+ dcache_enable();
+#endif
+
+ //
+ // TODO remove this hack. This is to set the wait states to max for Flash.
+ //
+#ifdef CONFIG_EP9301
+ HAL_WRITE_UINT32(0x80080018, 0x1000FFFF);
+#else
+ HAL_WRITE_UINT32(0x80080018, 0x2000FFFF);
+#endif // CONFIG_EP9301
+
+#if 0
+ //
+ // Set this bit like the Kernel expects it(runs serial off of the 14Mhz).
+ //
+ HAL_WRITE_UINT32(EP9312_PWRCNT, EP9312_PWRCNT_UARTBAUD);
+#endif
+
+
+ /* Machine number, as defined in linux/arch/arm/tools/mach-types */
+#if defined(CONFIG_EDB9301)
+ gd->bd->bi_arch_number = 462;
+
+#elif defined(CONFIG_EDB9302)
+ gd->bd->bi_arch_number = 538;
+
+#elif defined(CONFIG_EDB9307)
+ gd->bd->bi_arch_number = 607;
+
+#elif defined(CONFIG_EDB9312)
+ gd->bd->bi_arch_number = 451;
+
+#elif defined(CONFIG_EDB9315)
+ gd->bd->bi_arch_number = 463;
+
+#else
+#error "CONFIG_EDB93nn is not properly #define'd"
+#endif
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
+
+ /* We have a console */
+ gd->have_console = 1;
+
+ return(0);
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE_1;
+
+ return(0);
+}
diff -urP u-boot.orig-20060405/board/edb93xx/lowlevel_init.S
u-boot.scrubbed-20060405/board/edb93xx/lowlevel_init.S
--- u-boot.orig-20060405/board/edb93xx/lowlevel_init.S 1969-12-31
19:00:00.000000000 -0500
+++ u-boot.scrubbed-20060405/board/edb93xx/lowlevel_init.S 2006-04-05
09:47:47.000000000 -0400
@@ -0,0 +1,110 @@
+/*
+ * Memory Setup stuff - taken from Cirrus Logic EP9312 spec Revision 0.14
+ *
+ * Copyright (C) 2002 2003 Adam Bezanson, Network Audio Technologies, Inc.
+ * (bezanson@xxxxxxxxxxxxxxxx)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+
+#include <config.h>
+#include <version.h>
+#include <ep93xx.h>
+
+/* Include SDRAM stuff */
+#include "sdramcfg.S"
+
+
+
+.globl lowlevel_init
+lowlevel_init:
+
+ //
+ // Make sure caches are off
+ //
+ ldr r1,=0
+ mcr p15,0,r1,c1,c0,0
+ nop
+ nop
+ nop
+ nop
+
+ //
+ // Go back to running from the external clock.
+ //
+ ldr r1, =EP9312_CLKSET1
+ mov r0, #0
+ str r0, [r1]
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ //
+ // Turn off both LEDs
+ //
+ ldr r1, =EP9312_LED_DATA
+ ldr r0, [r1]
+
+ //
+ // Turn on both LEDs
+ //
+ orr r0, r0, #(EP9312_LED_GREEN_ON | EP9312_LED_RED_ON)
+ str r0, [r1]
+
+ //
+ // Turn off auto-precharge.
+ //
+ ldr r1, =EP9312_SDRAMCTRL
+ ldr r0, [r1,#EP9312_SDRAMCTRL_DEVCFG_3]
+ bic r0, r0, #EP9312_SDRAMCTRL_DEVCFG_AUTOPRE
+ str r0, [r1,#EP9312_SDRAMCTRL_DEVCFG_3]
+
+ //
+ // Turn off the Green LED and leave the Red LED on.
+ //
+ ldr r1, =EP9312_LED_DATA
+ ldr r0, [r1]
+ bic r0, r0, #(EP9312_LED_GREEN_ON)
+ str r0, [r1]
+
+
+ //
+ // Need to make sure that SDRAM is configured correctly before
+ // coping the code into it.
+ //
+ SdramCfg
+
+ nop
+ nop
+ nop
+ nop
+
+ //
+ // Turn on Green LED, Turn off the Red LED.
+ //
+ ldr r1, =EP9312_LED_DATA
+ ldr r0, [r1]
+ eor r0, r0, #(EP9312_LED_GREEN_ON | EP9312_LED_RED_ON)
+ strb r0,[r1]
+
+ mov pc,lr
diff -urP u-boot.orig-20060405/board/edb93xx/Makefile
u-boot.scrubbed-20060405/board/edb93xx/Makefile
--- u-boot.orig-20060405/board/edb93xx/Makefile 1969-12-31 19:00:00.000000000
-0500
+++ u-boot.scrubbed-20060405/board/edb93xx/Makefile 2006-04-05
09:47:47.000000000 -0400
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@xxxxxxxx
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := edb93xx.o
+SOBJS := lowlevel_init.o
+
+all: $(HDR) $(LIB)
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff -urP u-boot.orig-20060405/board/edb93xx/sdramcfg.S
u-boot.scrubbed-20060405/board/edb93xx/sdramcfg.S
--- u-boot.orig-20060405/board/edb93xx/sdramcfg.S 1969-12-31
19:00:00.000000000 -0500
+++ u-boot.scrubbed-20060405/board/edb93xx/sdramcfg.S 2006-04-05
09:47:47.000000000 -0400
@@ -0,0 +1,198 @@
+/*=============================================================================
+//
+// sdramcfg.h
+//
+// SDRAM Configuration Routine.
+//
+//=============================================================================
+//####COPYRIGHTBEGIN####
+//
+// -------------------------------------------
+// Copyright(c) Cirrus Logic Corporation 2003, All Rights Reserved
+// -------------------------------------------
+//
+//####COPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jordan
+// Contributors: rgorsegn
+// Date: 2003-08-15
+// Purpose: Cirrus Logic EP93xx SDRAM Config Routine
+// Description:
+// Usage: #include <cyg/hal/sdramcfg.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#define GLOBALCFG_INIT 0x00000001
+#define GLOBALCFG_MRS 0x00000002
+#define GLOBALCFG_SMEMBUSY 0x00000020
+#define GLOBALCFG_LCR 0x00000040
+#define GLOBALCFG_REARBEN 0x00000080
+#define GLOBALCFG_CLKSHUTDOWN 0x40000000
+#define GLOBALCFG_CKE 0x80000000
+
+#define REFRESH_MASK 0x0000FFFF
+
+#define BOOTSTATUS_WIDTH_32 0x00000002
+#define BOOTSTATUS_WIDTH_16 0x00000001
+#define BOOTSTATUS_WIDTH_8 0x00000000
+#define BOOTSTATUS_WIDTH_MASK 0x00000003
+#define BOOTSTATUS_MEDIA 0x00000004
+
+#define DEVCFG_EXTBUSWIDTH 0x00000004
+#define DEVCFG_BANKCOUNT 0x00000008
+#define DEVCFG_SROM512 0x00000010
+#define DEVCFG_SROMLL 0x00000020
+#define DEVCFG_2KPAGE 0x00000040
+#define DEVCFG_SFCONFIGADDR 0x00000080
+#define DEVCFG_CASLAT_MASK 0x00070000
+#define DEVCFG_CASLAT_2 0x00010000
+#define DEVCFG_CASLAT_3 0x00020000
+#define DEVCFG_CASLAT_4 0x00030000
+#define DEVCFG_CASLAT_5 0x00040000
+#define DEVCFG_CASLAT_6 0x00050000
+#define DEVCFG_CASLAT_7 0x00060000
+#define DEVCFG_CASLAT_8 0x00070000
+#define DEVCFG_WBL 0x00080000
+#define DEVCFG_RASTOCAS_MASK 0x00300000
+#define DEVCFG_RASTOCAS_2 0x00200000
+#define DEVCFG_RASTOCAS_3 0x00300000
+#define DEVCFG_AUTOPRECHARGE 0x01000000
+
+//****************************************************************************
+// Delay200 - Delays200 us
+//
+// Uses r0
+//****************************************************************************
+ .macro Delay200
+ mov r0, #64
+200:
+ subs r0, r0, #1
+ bne 200b
+ .endm
+
+//****************************************************************************
+// SdramCfg - Initialize SDRAM controller
+//
+// Uses r0
+//****************************************************************************
+ .macro SdramCfg
+ //
+ // Initialize the SDRAM Configuration
+ //
+#ifdef CONFIG_EP9301
+ ldr r0, =(DEVCFG_BANKCOUNT | DEVCFG_SROMLL | DEVCFG_CASLAT_3 | \
+ DEVCFG_RASTOCAS_3 | DEVCFG_EXTBUSWIDTH)
+#else
+ ldr r0, =(DEVCFG_BANKCOUNT | DEVCFG_SROMLL | DEVCFG_CASLAT_2 | \
+ DEVCFG_RASTOCAS_2)
+#endif // CONFIG_EP9301
+ ldr r1, =0x8006001C
+ str r0, [r1]
+
+ Delay200
+
+ //
+ // Set the Initialize and MRS bits (issue continuous NOP commands
+ // (INIT & MRS set))
+ //
+ ldr r0, =(GLOBALCFG_INIT | GLOBALCFG_MRS | GLOBALCFG_CKE)
+ ldr r1, =0x80060004
+ str r0, [r1]
+
+ Delay200
+
+ //
+ // Clear the MRS bit to issue a precharge all.
+ //
+ ldr r0, =(GLOBALCFG_INIT | GLOBALCFG_CKE)
+ str r0, [r1]
+
+ //
+ // Temporarily set the refresh timer to 0x10. Make it really low so that
+ // auto refresh cycles are generated. is refreshed.
+ //
+ ldr r0, =0x10
+ ldr r1, =0x80060008
+ str r0, [r1]
+
+ Delay200
+
+#ifdef CONFIG_EP9301
+ ldr r0, =0x204
+#else
+ ldr r0, =0x23
+#endif // CONFIG_EP9301
+ ldr r1, =0x80060008
+ str r0, [r1]
+
+ //
+ // Select mode register update mode
+ //
+ ldr r0, =(GLOBALCFG_CKE | GLOBALCFG_MRS)
+ ldr r1, =0x80060004
+ str r0, [r1]
+
+// *******************************************************************
+//
+// Program the SDRAM mode register using the row information.
+//
+// | | | |
+// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+// |13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+// +---------+------+ +---+--+ + +--+--+
+// | | | |
+// Must Be Zero | | |
+// | | |
+// | | |
+// LTMODE ---------------+ | |
+// | |
+// Wrap type ---------------------+ |
+// |
+// CAS Latency ---------------------------+
+//
+// *******************************************************************
+//
+// Row Column mapping for 256Meg X 16 Bits X 2.
+//
+// B1 B0 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
+//
+// Row/Bank A27 A26 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
+//
+// Col A27 A26 AP A25 A24 A09 A08 A07 A06 A05 A04 A03 A02
+//
+// *******************************************************************
+// Sets all four banks using - Cas latency 3
+// - Wrap type sequential
+// - Burst Length 4
+//
+// *******************************************************************
+#ifdef CONFIG_EP9301
+ mov r1, #0x0006600
+ ldr r0, [r1]
+#else
+ mov r1, #0x0008800
+ ldr r0, [r1]
+
+ ldr r1, =0x0400000
+ ldr r0, [r1]
+
+ ldr r1, =0x0808800
+ ldr r0, [r1]
+
+ ldr r1, =0x0c08800
+ ldr r0, [r1]
+#endif // CONFIG_EP9301
+
+ //
+ // Select mode register update mode
+ //
+ ldr r0, =GLOBALCFG_CKE
+ ldr r1, =0x80060004
+ str r0, [r1]
+
+ .endm
diff -urP u-boot.orig-20060405/board/edb93xx/u-boot.lds
u-boot.scrubbed-20060405/board/edb93xx/u-boot.lds
--- u-boot.orig-20060405/board/edb93xx/u-boot.lds 1969-12-31
19:00:00.000000000 -0500
+++ u-boot.scrubbed-20060405/board/edb93xx/u-boot.lds 2006-04-05
09:47:47.000000000 -0400
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@xxxxxxxx
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+/* board/edb93xx/header_revD0.o */
+ cpu/arm920t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff -urP u-boot.orig-20060405/config.mk u-boot.scrubbed-20060405/config.mk
--- u-boot.orig-20060405/config.mk 2006-04-04 09:55:28.000000000 -0400
+++ u-boot.scrubbed-20060405/config.mk 2006-04-05 09:47:49.000000000 -0400
@@ -94,7 +94,7 @@
# Option checker (courtesy linux kernel) to ensure
# only supported compiler options are used
#
-cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \
+cc-option = $(shell if $(CC) $(1) -S -o /dev/null -xc /dev/null \
> /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;)
#
diff -urP u-boot.orig-20060405/cpu/arm920t/ep93xx/cpu.c
u-boot.scrubbed-20060405/cpu/arm920t/ep93xx/cpu.c
--- u-boot.orig-20060405/cpu/arm920t/ep93xx/cpu.c 1969-12-31
19:00:00.000000000 -0500
+++ u-boot.scrubbed-20060405/cpu/arm920t/ep93xx/cpu.c 2006-04-05
09:47:42.000000000 -0400
@@ -0,0 +1,140 @@
+/* vim: set ts=8 sw=8 noet:
+ *
+ * Cirrus Logic EP93xx CPU-specific support.
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@xxxxxxxxxxxxxxxxxx>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+
+#if defined(CONFIG_EP93XX)
+#include <ep93xx.h>
+
+
+/* WARNING! WARNING! WARNING!
+ *
+ * The EP93xx family supposedly has support for chip type (i.e. 9301, 9302,
+ * 9312, etc.) and silicon revision determination. In practice, however,
+ * run-time determination of chip type via documented methods has proven
+ * impossible on all chip revisions (through E0) thus far due to silicon
+ * 'issues'.
+ *
+ * Perhaps this will change in the future; until then, use the autodetected
+ * chip type at your own risk!
+ *
+ * Note also that the chip revision indication found in the CHIP_ID register
+ * (0x80930094) has proven reliable for determining a particular core's
+ * silicon version.
+ *
+ * WARNING! WARNING! WARNING! */
+extern int checkcpu(void)
+{
+ printf("CPU: Cirrus Logic ");
+ switch (SecurityExtensionID & 0x000001FE) {
+ case 0x00000008:
+ printf("EP9301");
+ break;
+
+ case 0x00000004:
+ printf("EP9312");
+ break;
+
+ case 0x00000000:
+ printf("EP9315");
+ break;
+
+ default:
+ printf("<unknown>");
+ break;
+ }
+
+ printf(" - Rev. ");
+ switch (SysconCHIP_ID & 0xF0000000) {
+ case 0x00000000:
+ printf("A");
+ break;
+
+ case 0x10000000:
+ printf("B");
+ break;
+
+ case 0x20000000:
+ printf("C");
+ break;
+
+ case 0x30000000:
+ printf("D0");
+ break;
+
+ case 0x40000000:
+ printf("D1");
+ break;
+
+ case 0x50000000:
+ printf("E0");
+ break;
+
+ default:
+ printf("?");
+ break;
+ }
+ printf("\n");
+
+ return(0);
+}
+
+
+/* All EP93xx variants have 16 KiB I-cache. */
+extern int checkicache(void)
+{
+ return(16 << 10);
+}
+
+
+/* All EP93xx variants have 16 KiB D-cache. */
+extern int checkdcache(void)
+{
+ return(16 << 10);
+}
+
+
+/* This is a nop on ARM, and is included here for completeness only. */
+extern void upmconfig(unsigned int upm, unsigned int *table, unsigned int size)
+{
+ /* nop */
+}
+
+
+/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
+extern void reset_cpu(ulong addr)
+{
+ /* Unlock DeviceCfg and write '1' */
+ SYSCON_SW_UNCLOCK;
+ SysconDEVCFG |= (1 << 31);
+
+ /* Unlock DeviceCfg and write '0' */
+ SYSCON_SW_UNCLOCK;
+ SysconDEVCFG &= ~(1 << 31);
+
+ /* Dying... */
+ while(1);
+}
+
+
+#endif /* defined(CONFIG_EP93XX) */
diff -urP u-boot.orig-20060405/cpu/arm920t/ep93xx/eth.c
u-boot.scrubbed-20060405/cpu/arm920t/ep93xx/eth.c
--- u-boot.orig-20060405/cpu/arm920t/ep93xx/eth.c 1969-12-31
19:00:00.000000000 -0500
+++ u-boot.scrubbed-20060405/cpu/arm920t/ep93xx/eth.c 2006-04-05
09:47:42.000000000 -0400
@@ -0,0 +1,917 @@
+/* vim: set ts=8 sw=8 noet:
+ *
+ * Cirrus Logic EP93xx ethernet MAC / MII driver.
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@xxxxxxxxxxxxxxxxxx>
+ *
+ * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
+ * which is
+ *
+ * (C) Copyright 2002 2003
+ * Adam Bezanson, Network Audio Technologies, Inc.
+ * <bezanson@xxxxxxxxxxxxxxxx>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <command.h>
+#include <common.h>
+#include <ep93xx.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <net.h>
+#include <linux/types.h>
+
+
+/**
+ * Send an error message to the terminal.
+ */
+#define ERROR(x) \
+do { \
+ char *__foo = strrchr(__FILE__, '/'); \
+ \
+ printf("%s: %d: %s(): ", (__foo == NULL ? __FILE__ : (__foo + 1)), \
+ __LINE__, __FUNCTION__); \
+ printf x; printf("\n"); \
+} while (0);
+
+
+/**
+ * Send a trace message to the terminal.
+ */
+#if 0
+#define TRACE(x) \
+do { \
+ char *__foo = strrchr(__FILE__, '/'); \
+ \
+ printf("%s: %d: %s(): ", (__foo == NULL ? __FILE__ : (__foo + 1)), \
+ __LINE__, __FUNCTION__); \
+ printf x; printf("\n"); \
+} while (0);
+
+#else
+#define TRACE(x)
+#endif
+
+
+/*
-----------------------------------------------------------------------------
+ * EP93xx ethernet MAC functionality
+ */
+#if defined(CONFIG_DRIVER_EP93XX_MAC)
+
+/**
+ * #define this to dump device status and queue info during initialization and
+ * following errors.
+ */
+#undef EP93XX_MAC_DEBUG
+
+/**
+ * Number of descriptor and status entries in our RX queues.
+ */
+#define NUMRXDESC (8)
+
+/**
+ * Number of descriptor and status entries in our TX queues.
+ */
+#define NUMTXDESC (1)
+
+/**
+ * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
+ */
+#define TXSTARTMAX (944)
+
+
+/**
+ * Ethernet MAC interface return values for public functions.
+ */
+enum eth_status {
+ ETH_STATUS_SUCCESS = 0,
+ ETH_STATUS_FAILURE = 1,
+};
+
+
+/**
+ * Receive descriptor queue entry
+ */
+struct rx_descriptor_t {
+ union {
+ uint32_t word1;
+
+ struct {
+ unsigned buffer_address : 32;
+ };
+ };
+
+ union {
+ uint32_t word2;
+
+ struct {
+ unsigned buffer_length : 16;
+ unsigned buffer_index : 15;
+ unsigned not_sof : 1;
+ };
+ };
+} __attribute__((packed));
+
+typedef struct rx_descriptor_t rx_descriptor_t;
+
+
+/**
+ * Receive status queue entry
+ */
+struct rx_status_t {
+ union {
+ uint32_t word1;
+
+ struct {
+ unsigned : 8;
+ unsigned hti : 6;
+ unsigned : 1;
+ unsigned crci : 1;
+ unsigned crce : 1;
+ unsigned edata : 1;
+ unsigned runt : 1;
+ unsigned fe : 1;
+ unsigned oe : 1;
+ unsigned rx_err : 1;
+ unsigned am : 2;
+ unsigned : 4;
+ unsigned eob : 1;
+ unsigned eof : 1;
+ unsigned rwe : 1;
+ unsigned rfp : 1;
+ };
+ };
+
+ union {
+ uint32_t word2;
+
+ struct {
+ unsigned frame_length : 16;
+ unsigned buffer_index : 15;
+ unsigned rfp : 1;
+ };
+ };
+} __attribute__((packed));
+
+typedef struct rx_status_t rx_status_t;
+
+
+/**
+ * Transmit descriptor queue entry
+ */
+struct tx_descriptor_t
+{
+ union {
+ uint32_t word1;
+
+ struct {
+ unsigned buffer_address : 32;
+ };
+ };
+
+ union {
+ uint32_t word2;
+
+ struct {
+ unsigned buffer_length : 12;
+ unsigned : 3;
+ unsigned abort_frame : 1;
+ unsigned buffer_index : 15;
+ unsigned eof : 1;
+ };
+ };
+} __attribute__((packed));
+
+typedef struct tx_descriptor_t tx_descriptor_t;
+
+
+/**
+ * Transmit status queue entry
+ */
+struct tx_status_t {
+ union {
+ uint32_t word1;
+
+ struct {
+ unsigned tbi : 15;
+ unsigned : 1;
+ unsigned ncoll : 5;
+ unsigned : 3;
+ unsigned ecoll : 1;
+ unsigned txu : 1;
+ unsigned ow : 1;
+ unsigned : 1;
+ unsigned lcrs : 1;
+ unsigned fa : 1;
+ unsigned txwe : 1;
+ unsigned txfp : 1;
+ };
+ };
+} __attribute__((packed));
+
+typedef struct tx_status_t tx_status_t;
+
+
+/**
+ * Transmit descriptor queue
+ */
+struct tx_descriptor_queue_t {
+ tx_descriptor_t *base;
+ tx_descriptor_t *current;
+ tx_descriptor_t *end;
+};
+
+typedef struct tx_descriptor_queue_t tx_descriptor_queue_t;
+
+
+/**
+ * Transmit status queue
+ */
+struct tx_status_queue_t {
+ tx_status_t *base;
+ tx_status_t *current;
+ tx_status_t *end;
+};
+
+typedef struct tx_status_queue_t tx_status_queue_t;
+
+
+/**
+ * Receive descriptor queue
+ */
+struct rx_descriptor_queue_t {
+ rx_descriptor_t *base;
+ rx_descriptor_t *current;
+ rx_descriptor_t *end;
+};
+
+typedef struct rx_descriptor_queue_t rx_descriptor_queue_t;
+
+
+/**
+ * Receive status queue
+ */
+struct rx_status_queue_t {
+ rx_status_t *base;
+ rx_status_t *current;
+ rx_status_t *end;
+};
+
+typedef struct rx_status_queue_t rx_status_queue_t;
+
+
+/**
+ * EP93xx MAC private data structure
+ */
+struct ep93xx_mac {
+ int is_initialized;
+
+ rx_descriptor_queue_t rx_dq;
+ rx_status_queue_t rx_sq;
+ void * rx_buffer[NUMRXDESC];
+
+ tx_descriptor_queue_t tx_dq;
+ tx_status_queue_t tx_sq;
+};
+
+
+/* ep93xx_miiphy ops forward declarations */
+static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
+ unsigned char const reg, unsigned short * const value);
+static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
+ unsigned char const reg, unsigned short const value);
+
+
+/* Reserve memory for the MAC's private data */
+static struct ep93xx_mac dev = { 0 };
+
+
+/**
+ * Dump ep93xx_mac values to the terminal.
+ */
+extern inline void dump_dev(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+ int i;
+
+ printf("\ndump_dev()\n");
+ printf(" is_initialized %02X\n", dev.is_initialized);
+ printf(" rx_dq.base %08X\n", dev.rx_dq.base);
+ printf(" rx_dq.current %08X\n", dev.rx_dq.current);
+ printf(" rx_dq.end %08X\n", dev.rx_dq.end);
+ printf(" rx_sq.base %08X\n", dev.rx_sq.base);
+ printf(" rx_sq.current %08X\n", dev.rx_sq.current);
+ printf(" rx_sq.end %08X\n", dev.rx_sq.end);
+
+ for (i = 0; i < NUMRXDESC; i++) {
+ printf(" rx_buffer[%2.d] %08X\n", i, dev.rx_buffer[i]);
+ }
+
+ printf(" tx_dq.base %08X\n", dev.tx_dq.base);
+ printf(" tx_dq.current %08X\n", dev.tx_dq.current);
+ printf(" tx_dq.end %08X\n", dev.tx_dq.end);
+ printf(" tx_sq.base %08X\n", dev.tx_sq.base);
+ printf(" tx_sq.current %08X\n", dev.tx_sq.current);
+ printf(" tx_sq.end %08X\n", dev.tx_sq.end);
+#endif /* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Dump all RX descriptor queue entries to the terminal.
+ */
+extern inline void dump_rx_descriptor_queue(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+ int i;
+
+ printf("\ndump_rx_descriptor_queue()\n");
+ printf(" descriptor address word1 word2\n");
+ for (i = 0; i < NUMRXDESC; i++) {
+ printf(" [ %08X ] %08X %08X\n",
+ (dev.rx_dq.base + i),
+ (dev.rx_dq.base + i)->word1,
+ (dev.rx_dq.base + i)->word2);
+ }
+#endif /* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Dump all RX status queue entries to the terminal.
+ */
+extern inline void dump_rx_status_queue(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+ int i;
+
+ printf("\ndump_rx_status_queue()\n");
+ printf(" descriptor address word1 word2\n");
+ for (i = 0; i < NUMRXDESC; i++) {
+ printf(" [ %08X ] %08X %08X\n",
+ (dev.rx_sq.base + i),
+ (dev.rx_sq.base + i)->word1,
+ (dev.rx_sq.base + i)->word2);
+ }
+#endif /* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Dump all TX descriptor queue entries to the terminal.
+ */
+extern inline void dump_tx_descriptor_queue(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+ int i;
+
+ printf("\ndump_tx_descriptor_queue()\n");
+ printf(" descriptor address word1 word2\n");
+ for (i = 0; i < NUMTXDESC; i++) {
+ printf(" [ %08X ] %08X %08X\n",
+ (dev.tx_dq.base + i),
+ (dev.tx_dq.base + i)->word1,
+ (dev.tx_dq.base + i)->word2);
+ }
+#endif /* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Dump all TX status queue entries to the terminal.
+ */
+extern inline void dump_tx_status_queue(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+ int i;
+
+ printf("\ndump_tx_status_queue()\n");
+ printf(" descriptor address word1\n");
+ for (i = 0; i < NUMTXDESC; i++) {
+ printf(" [ %08X ] %08X\n",
+ (dev.rx_sq.base + i),
+ (dev.rx_sq.base + i)->word1);
+ }
+#endif /* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
+ * it's cleared.
+ */
+static void ep93xx_mac_reset(void)
+{
+ TRACE(("+ep93xx_mac_reset"));
+
+ OpReg_SelfCTL |= SelfCTL_RESET;
+ while (OpReg_SelfCTL & SelfCTL_RESET) {
+ /* nop */
+ }
+
+ TRACE(("-ep93xx_mac_reset"));
+}
+
+
+/**
+ * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
+ * registers.
+ */
+extern void eth_halt(void)
+{
+ TRACE(("+eth_halt"));
+
+ OpReg_RxCTL = 0x00000000;
+ OpReg_TxCTL = 0x00000000;
+
+ TRACE(("-eth_halt"));
+}
+
+
+/**
+ * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are
+ * allocated, if necessary, for the TX and RX descriptor and status queues,
+ * as well as for received packets. The EP93XX MAC hardware is initialized.
+ * Transmit and receive operations are enabled.
+ */
+extern int eth_init(bd_t * const bd)
+{
+ int ret = ETH_STATUS_FAILURE;
+ int i;
+
+ TRACE(("+eth_init"));
+
+ /* Parameter check */
+ if (bd == NULL) {
+ ERROR(("NULL bd"));
+ goto eth_init_failed_0;
+ }
+
+ /* Reset the MAC */
+ ep93xx_mac_reset();
+
+ /* Allocate space for the queues and RX packet buffers if we're not
+ * already initialized */
+ if (!dev.is_initialized) {
+ if ((dev.tx_dq.base = calloc(NUMTXDESC,
+ sizeof(tx_descriptor_t))) == NULL) {
+ ERROR(("calloc() failed"));
+ goto eth_init_failed_0;
+ }
+
+ if ((dev.tx_sq.base = calloc(NUMTXDESC,
+ sizeof(tx_status_t))) == NULL) {
+ ERROR(("calloc() failed"));
+ goto eth_init_failed_1;
+ }
+
+ if ((dev.rx_dq.base = calloc(NUMRXDESC,
+ sizeof(rx_descriptor_t))) == NULL) {
+ ERROR(("calloc() failed"));
+ goto eth_init_failed_2;
+ }
+
+ if ((dev.rx_sq.base = calloc(NUMRXDESC,
+ sizeof(rx_status_t))) == NULL) {
+ ERROR(("calloc() failed"));
+ goto eth_init_failed_3;
+ }
+
+ for (i = 0; i < NUMRXDESC; i++) {
+ dev.rx_buffer[i] = NULL;
+ }
+
+ for (i = 0; i < NUMRXDESC; i++) {
+ if ((dev.rx_buffer[i] = calloc(1, PKTSIZE)) == NULL) {
+ ERROR(("calloc() failed"));
+ goto eth_init_failed_4;
+ }
+ }
+
+ /* Set is_initialized flag so we don't go through allocation
+ * portion of init again. */
+ dev.is_initialized = 1;
+ }
+
+ /* Reset the descriptor queues' current and end address values */
+ dev.tx_dq.current = dev.tx_dq.base;
+ dev.tx_dq.end = (dev.tx_dq.base + NUMTXDESC);
+
+ dev.tx_sq.current = dev.tx_sq.base;
+ dev.tx_sq.end = (dev.tx_sq.base + NUMTXDESC);
+
+ dev.rx_dq.current = dev.rx_dq.base;
+ dev.rx_dq.end = (dev.rx_dq.base + NUMRXDESC);
+
+ dev.rx_sq.current = dev.rx_sq.base;
+ dev.rx_sq.end = (dev.rx_sq.base + NUMRXDESC);
+
+ /* Set the transmit descriptor and status queues' base address,
+ * current address, and length registers. Set the maximum frame
+ * length and threshold. Enable the transmit descriptor processor. */
+ OpReg_TxDBA = (uint32_t)dev.tx_dq.base;
+ OpReg_TxDCA = (uint32_t)dev.tx_dq.base;
+ OpReg_TxDBL = (sizeof(tx_descriptor_t) * NUMTXDESC);
+
+ OpReg_TxSBA = (uint32_t)dev.tx_sq.base;
+ OpReg_TxSCA = (uint32_t)dev.tx_sq.base;
+ OpReg_TxSBL = (sizeof(tx_status_t) * NUMTXDESC);
+
+ OpReg_MaxFL = (TXSTARTMAX << 16) | (PKTSIZE << 0);
+ OpReg_BMCTL = BMCTL_TxEn;
+
+ /* Set the receive descriptor and status queues' base address,
+ * current address, and length registers. Enable the receive
+ * descriptor processor. */
+ OpReg_RxDBA = (uint32_t)dev.rx_dq.base;
+ OpReg_RxDCA = (uint32_t)dev.rx_dq.base;
+ OpReg_RxDBL = (sizeof(rx_descriptor_t) * NUMRXDESC);
+
+ OpReg_RxSBA = (uint32_t)dev.rx_sq.base;
+ OpReg_RxSCA = (uint32_t)dev.rx_sq.base;
+ OpReg_RxSBL = (sizeof(rx_status_t) * NUMRXDESC);
+
+ OpReg_BMCTL = BMCTL_RxEn;
+
+ /* Wait until the receive descriptor processor is active */
+ while (!(OpReg_BMSts & BMSts_RxAct)) {
+ /* nop */
+ }
+
+ /* Initialize the RX descriptor queue. Clear the TX descriptor queue.
+ * Clear the RX and TX status queues. Enqueue the RX descriptor and
+ * status entries to the MAC. */
+ for (i = 0; i < NUMRXDESC; i++) {
+ (dev.rx_dq.base + i)->buffer_address =
+ (uint32_t)dev.rx_buffer[i];
+ (dev.rx_dq.base + i)->buffer_length = PKTSIZE;
+ (dev.rx_dq.base + i)->buffer_index = 0;
+ }
+
+ memset(dev.tx_dq.base, 0, (sizeof(tx_descriptor_t) * NUMTXDESC));
+ memset(dev.rx_sq.base, 0, (sizeof(rx_status_t) * NUMRXDESC));
+ memset(dev.tx_sq.base, 0, (sizeof(tx_status_t) * NUMTXDESC));
+
+ OpReg_RxDEQ = NUMRXDESC;
+ OpReg_RxSEQ = NUMRXDESC;
+
+ /* Set the primary MAC address */
+ OpReg_AFP = AFP_IAPrimary;
+ OpReg_IndAd = (bd->bi_enetaddr[0] |
+ (bd->bi_enetaddr[1] << 8) |
+ (bd->bi_enetaddr[2] << 16) |
+ (bd->bi_enetaddr[3] << 24));
+ OpReg_IndAd1 = (bd->bi_enetaddr[4] | (bd->bi_enetaddr[5] << 8));
+
+ /* Turn on RX and TX */
+ OpReg_RxCTL = (RxCTL_IndividualAccept0 | RxCTL_BroadcastA |
+ RxCTL_SerRxON);
+ OpReg_TxCTL = TxCTL_SerTxON;
+
+ /* Dump data structures if we're debugging */
+ dump_dev();
+ dump_rx_descriptor_queue();
+ dump_rx_status_queue();
+ dump_tx_descriptor_queue();
+ dump_tx_status_queue();
+
+#if defined(CONFIG_MII)
+ miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write);
+#endif
+
+ /* Done! */
+ ret = ETH_STATUS_SUCCESS;
+ goto eth_init_done;
+
+eth_init_failed_4:
+ for (i = 0; i < NUMRXDESC; i++) {
+ if (dev.rx_buffer[i] != NULL) {
+ free(dev.rx_buffer[i]);
+ }
+ }
+
+ free(dev.rx_sq.base);
+ /* Fall through */
+
+eth_init_failed_3:
+ free(dev.rx_dq.base);
+ /* Fall through */
+
+eth_init_failed_2:
+ free(dev.tx_sq.base);
+ /* Fall through */
+
+eth_init_failed_1:
+ free(dev.tx_dq.base);
+ /* Fall through */
+
+eth_init_failed_0:
+eth_init_done:
+ TRACE(("-eth_init %d", ret));
+ return(ret);
+}
+
+
+/**
+ * Copy a frame of data from the MAC into the protocol layer for further
+ * processing.
+ *
+ * TODO: Enhance this to deal with as many packets as are available at
+ * the MAC at one time? */
+extern int eth_rx(void)
+{
+ int ret = ETH_STATUS_FAILURE;
+ int nbytes_frame = 0;
+ int nbytes_fragment = 0;
+ void *dest = (void *)NetRxPackets[0];
+
+ TRACE(("+eth_rx"));
+
+ while (1) {
+ if (dev.rx_sq.current->rfp && dev.rx_sq.current->rwe) {
+ /* We have a good frame. Extract the frame's length
+ * from the current rx_status_queue entry, and copy
+ * the frame's data into NetRxPackets[] of the
+ * protocol stack. We track the total number of
+ * bytes in the frame (nbytes_frame) which will be
+ * used when we pass the data off to the protocol
+ * layer via NetReceive(). */
+ nbytes_fragment = dev.rx_sq.current->frame_length;
+ nbytes_frame += nbytes_fragment;
+
+ memcpy(dest, (void *)dev.rx_dq.current->buffer_address,
+ nbytes_fragment);
+ dest += nbytes_fragment;
+
+ /* Clear the associated status queue entry, and
+ * increment our current pointers to the next RX
+ * descriptor and status queue entries (making sure
+ * we wrap properly). */
+ memset(dev.rx_sq.current, 0, sizeof(rx_status_t));
+
+ dev.rx_sq.current++;
+ if (dev.rx_sq.current >= dev.rx_sq.end)
+ dev.rx_sq.current = dev.rx_sq.base;
+
+ dev.rx_dq.current++;
+ if (dev.rx_dq.current >= dev.rx_dq.end) {
+ dev.rx_dq.current = dev.rx_dq.base;
+ }
+
+ /* Finally, return the RX descriptor and status entries
+ * back to the MAC engine, and loop again, checking for
+ * more descriptors to process. */
+ OpReg_RxDEQ = 1;
+ OpReg_RxSEQ = 1;
+
+ } else if (!dev.rx_sq.current->rfp && !dev.rx_sq.current->rwe) {
+ /* We've no further queued descriptors. If data have
+ * been copied into the protocol layer, issue a
+ * NetReceive() call to pass the data to the protocol
+ * stack for further processing, and return
+ * successfully. */
+ if (nbytes_frame > 0) {
+ NetReceive(NetRxPackets[0], nbytes_frame);
+ TRACE(("reporting %d bytes (last: %d)...\n",
+ nbytes_frame, nbytes_fragment));
+ }
+
+ ret = ETH_STATUS_SUCCESS;
+ break;
+
+ } else {
+ /* Do we have an erroneous packet? */
+ ERROR(("packet rx error, status %08X %08X",
+ dev.rx_sq.current->word1,
+ dev.rx_sq.current->word2));
+ dump_rx_descriptor_queue();
+ dump_rx_status_queue();
+
+ /* TODO: Add better error handling? */
+ break;
+ }
+ }
+
+ TRACE(("-eth_rx %d", ret));
+ return(ret);
+}
+
+
+/**
+ * Send a block of data via ethernet.
+ *
+ * TODO: Enhance this to deal with as much data as are available at one time?
*/
+extern int eth_send(volatile void * const packet, int const length)
+{
+ int ret = ETH_STATUS_FAILURE;
+
+ TRACE(("+eth_send"));
+
+ /* Parameter check */
+ if (packet == NULL) {
+ ERROR(("NULL packet"));
+ goto eth_send_failed_0;
+ }
+
+ /* Initialize the TX descriptor queue with the new packet's info.
+ * Clear the associated status queue entry. Enqueue the packet
+ * to the MAC for transmission. */
+ dev.tx_dq.current->buffer_address = (uint32_t)packet;
+ dev.tx_dq.current->buffer_length = length;
+ dev.tx_dq.current->buffer_index = 0;
+ dev.tx_dq.current->eof = 1;
+
+ dev.tx_sq.current->word1 = 0;
+
+ OpReg_TxDEQ = 1;
+
+ /* Wait for TX to complete, and check status entry for errors. */
+ while (!(OpReg_IntStsC & IntSts_TxStsQ)) {
+ /* nop */
+ }
+
+ if (!dev.tx_sq.current->txfp || !dev.tx_sq.current->txwe) {
+ ERROR(("packet tx error, status %08X",
+ dev.tx_sq.current->word1));
+ dump_tx_descriptor_queue();
+ dump_tx_status_queue();
+
+ /* TODO: Add better error handling? */
+ goto eth_send_failed_0;
+ }
+
+ ret = ETH_STATUS_SUCCESS;
+ /* Fall through */
+
+eth_send_failed_0:
+ TRACE(("-eth_send %d", ret));
+ return(ret);
+}
+#endif /* defined(CONFIG_DRIVER_EP93XX_MAC) */
+
+
+/*
-----------------------------------------------------------------------------
+ * EP93xx ethernet MII functionality.
+ */
+#if defined(CONFIG_MII)
+
+/**
+ * Maximum MII address we support
+ */
+#define MII_ADDRESS_MAX (31)
+
+/**
+ * Maximum MII register address we support
+ */
+#define MII_REGISTER_MAX (31)
+
+
+/**
+ * Ethernet MII interface return values for public functions.
+ */
+enum mii_status {
+ MII_STATUS_SUCCESS = 0,
+ MII_STATUS_FAILURE = 1,
+};
+
+
+/**
+ * Read a 16-bit value from an MII register.
+ */
+static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
+ unsigned char const reg, unsigned short * const value)
+{
+ int ret = MII_STATUS_FAILURE;
+ uint32_t self_ctl;
+
+ TRACE(("+ep93xx_miiphy_read"));
+
+ /* Parameter checks */
+ if (dev == NULL) {
+ ERROR(("NULL dev"));
+ goto ep93xx_miiphy_read_failed_0;
+ }
+
+ if (addr > MII_ADDRESS_MAX) {
+ ERROR(("invalid addr, 0x%02X", addr));
+ goto ep93xx_miiphy_read_failed_0;
+ }
+
+ if (reg > MII_REGISTER_MAX) {
+ ERROR(("invalid reg, 0x%02X", reg));
+ goto ep93xx_miiphy_read_failed_0;
+ }
+
+ if (value == NULL) {
+ ERROR(("NULL value"));
+ goto ep93xx_miiphy_read_failed_0;
+ }
+
+ /* Save the current SelfCTL register value. Set MAC to suppress
+ * preamble bits. Wait for any previous MII command to complete
+ * before issuing the new command. */
+ self_ctl = OpReg_SelfCTL;
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
+ OpReg_SelfCTL = (self_ctl & ~(1 << 8));
+#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+ while (OpReg_MIISts & MIISts_Busy) {
+ /* nop */
+ }
+
+ /* Issue the MII 'read' command. Wait for the command to complete.
+ * Read the MII data value. */
+ OpReg_MIICmd = (MIICmd_Opcode_Read | ((uint32_t)addr << 5) |
+ (uint32_t)reg);
+ while (OpReg_MIISts & MIISts_Busy) {
+ /* nop */
+ }
+
+ *value = (unsigned short)OpReg_MIIData;
+
+ /* Restore the saved SelfCTL value and return. */
+ OpReg_SelfCTL = self_ctl;
+
+ ret = MII_STATUS_SUCCESS;
+ /* Fall through */
+
+ep93xx_miiphy_read_failed_0:
+ TRACE(("-ep93xx_miiphy_read"));
+ return(ret);
+}
+
+
+/**
+ * Write a 16-bit value to an MII register.
+ */
+static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
+ unsigned char const reg, unsigned short const value)
+{
+ int ret = MII_STATUS_FAILURE;
+ uint32_t self_ctl;
+
+ TRACE(("+ep93xx_miiphy_write"));
+
+ /* Parameter checks */
+ if (dev == NULL) {
+ ERROR(("NULL dev"));
+ goto ep93xx_miiphy_write_failed_0;
+ }
+
+ if (addr > MII_ADDRESS_MAX) {
+ ERROR(("invalid addr, 0x%02X", addr));
+ goto ep93xx_miiphy_write_failed_0;
+ }
+
+ if (reg > MII_REGISTER_MAX) {
+ ERROR(("invalid reg, 0x%02X", reg));
+ goto ep93xx_miiphy_write_failed_0;
+ }
+
+ /* Save the current SelfCTL register value. Set MAC to suppress
+ * preamble bits. Wait for any previous MII command to complete
+ * before issuing the new command. */
+ self_ctl = OpReg_SelfCTL;
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
+ OpReg_SelfCTL = (self_ctl & ~(1 << 8));
+#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+ while (OpReg_MIISts & MIISts_Busy) {
+ /* nop */
+ }
+
+ /* Issue the MII 'write' command. Wait for the command to complete. */
+ OpReg_MIIData = (uint32_t)value;
+ OpReg_MIICmd = (MIICmd_Opcode_Write | ((uint32_t)addr << 5) |
+ (uint32_t)reg);
+ while (OpReg_MIISts & MIISts_Busy) {
+ /* nop */
+ }
+
+ /* Restore the saved SelfCTL value and return. */
+ OpReg_SelfCTL = self_ctl;
+
+ ret = MII_STATUS_SUCCESS;
+ /* Fall through */
+
+ep93xx_miiphy_write_failed_0:
+ TRACE(("-ep93xx_miiphy_write"));
+ return(ret);
+}
+#endif /* defined(CONFIG_MII) */
+
diff -urP u-boot.orig-20060405/cpu/arm920t/ep93xx/interrupts.c
u-boot.scrubbed-20060405/cpu/arm920t/ep93xx/interrupts.c
--- u-boot.orig-20060405/cpu/arm920t/ep93xx/interrupts.c 1969-12-31
19:00:00.000000000 -0500
+++ u-boot.scrubbed-20060405/cpu/arm920t/ep93xx/interrupts.c 2006-04-05
09:47:42.000000000 -0400
@@ -0,0 +1,172 @@
+/* vim: set ts=8 sw=8 noet:
+ *
+ * Cirrus Logic EP93xx interrupt support.
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@xxxxxxxxxxxxxxxxxx>
+ *
+ * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
+ * author unknown.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+
+#if defined(CONFIG_EP93XX)
+#include <linux/types.h>
+#include <ep93xx.h>
+
+
+
+int interrupt_init(void);
+void reset_timer(void);
+ulong get_timer(ulong base);
+void set_timer(ulong t);
+void udelay(unsigned long usec);
+void reset_timer_masked(void);
+ulong get_timer_masked(void);
+void udelay_masked(unsigned long usec);
+unsigned long long get_ticks(void);
+ulong get_tbclk(void);
+
+
+int timer_load_val = 0;
+
+/* macro to read the 16 bit timer */
+static inline ulong READ_TIMER(void)
+{
+ return(Timer1Value & 0xffff);
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+
+/**
+ * Initialize interrupt support.
+ */
+int interrupt_init(void)
+{
+ Timer1Control = 0x00; /* use timer 1 with 2KHz and free running */
+ if (timer_load_val == 0) {
+ /*
+ * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
+ * (default) and prescaler = 16. Should be 10390
+ * @33.25MHz and 15625 @ 50 MHz
+ */
+ timer_load_val = 21; /* set to constant just now, until I
resolve clocking issues */
+ }
+ /* auto load, manual update of Timer 1 */
+ lastdec = Timer1Load = timer_load_val;
+ Timer1Control = 0xC0; /* Enable the timer and periodic mode*/
+
+ return(0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+void udelay(unsigned long usec)
+{
+ ulong tmo;
+
+ tmo = usec / 1000;
+ tmo *= (timer_load_val * 100);
+ tmo /= 1000;
+
+ tmo += get_timer(0);
+
+ while (get_timer_masked() < tmo)
+ /*NOP*/;
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = READ_TIMER();
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = READ_TIMER();
+
+ if (lastdec >= now) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec + timer_load_val - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+void udelay_masked(unsigned long usec)
+{
+ ulong tmo;
+
+ tmo = usec / 1000;
+ tmo *= (timer_load_val * 100);
+ tmo /= 1000;
+
+ reset_timer_masked();
+
+ while (get_timer_masked() < tmo)
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ ulong tbclk;
+
+ tbclk = timer_load_val * 100;
+ return tbclk;
+}
+
+
+#endif /* defined(CONFIG_EP93XX) */
diff -urP u-boot.orig-20060405/cpu/arm920t/ep93xx/Makefile
u-boot.scrubbed-20060405/cpu/arm920t/ep93xx/Makefile
--- u-boot.orig-20060405/cpu/arm920t/ep93xx/Makefile 1969-12-31
19:00:00.000000000 -0500
+++ u-boot.scrubbed-20060405/cpu/arm920t/ep93xx/Makefile 2006-04-05
09:47:42.000000000 -0400
@@ -0,0 +1,46 @@
+# vim: set ts=8 sw=8 noet:
+#
+# Cirrus Logic EP93xx CPU-specific Makefile
+#
+# Copyright (C) 2004, 2005
+# Cory T. Tusar, Videon Central, Inc., <ctusar@xxxxxxxxxxxxxxxxxx>
+#
+# Based on an original Makefile, which is
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@xxxxxxxx
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+include $(TOPDIR)/config.mk
+
+LIB = lib$(SOC).a
+OBJS = cpu.o eth.o interrupts.o serial.o speed.o
+
+
+all: .depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+
+#########################################################################
+.depend: Makefile $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+#########################################################################
diff -urP u-boot.orig-20060405/cpu/arm920t/ep93xx/serial.c
u-boot.scrubbed-20060405/cpu/arm920t/ep93xx/serial.c
--- u-boot.orig-20060405/cpu/arm920t/ep93xx/serial.c 1969-12-31
19:00:00.000000000 -0500
+++ u-boot.scrubbed-20060405/cpu/arm920t/ep93xx/serial.c 2006-04-05
09:47:42.000000000 -0400
@@ -0,0 +1,136 @@
+/* vim: set ts=8 sw=8 noet:
+ *
+ * Cirrus Logic EP93xx UART driver.
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@xxxxxxxxxxxxxxxxxx>
+ *
+ * Based on the original serial.c, which is
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@xxxxxxx>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <ep93xx.h>
+
+
+void serial_setbrg (void)
+{
+ /*DECLARE_GLOBAL_DATA_PTR;*/
+
+ int i;
+ /*unsigned int reg = 0; */
+ /* reg = get_UART_PCLK() / (16 * gd->baudrate) -1; */
+
+ SysconDEVCFG = 0x40000; /* enable UART1 */
+ rUART1_LCR_L = 0x3;
+ rUART1_LCR_M = 0x0;
+ rUART1_LCR_H = 0x60; /* FIFO Disable, 8 bits, 1 stop, no parity */
+ rUART1_CR = 0x31; /* UART Enable, TX/RX int enable, disable timeout int
*/
+
+ for (i = 0; i < 100; i++);
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int serial_init (void)
+{
+ serial_setbrg ();
+
+ return (0);
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_getc (void)
+{
+
+ while (!(rUART1_IIR & 0x2));
+ return rUART1_DR & 0xff;
+}
+
+#ifdef CONFIG_HWFLOW
+static int hwflow = 0; /* turned off by default */
+int hwflow_onoff(int on)
+{
+ switch(on) {
+ case 0:
+ default:
+ break; /* return current */
+ case 1:
+ hwflow = 1; /* turn on */
+ break;
+ case -1:
+ hwflow = 0; /* turn off */
+ break;
+ }
+ return hwflow;
+}
+#endif
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int be_quiet = 0;
+void disable_putc(void)
+{
+ be_quiet = 1;
+}
+
+void enable_putc(void)
+{
+ be_quiet = 0;
+}
+#endif
+
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc (const char c)
+{
+ /* wait for room in the tx FIFO */
+ while(rUART1_FR & 0x20);
+ rUART1_DR = c;
+
+ /* If \n, also do \r */
+ if (c == '\n')
+ serial_putc ('\r');
+}
+
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+int serial_tstc (void)
+{
+ return (!(rUART1_FR & 0x10));
+}
+
+void
+serial_puts (const char *s)
+{
+ while (*s) {
+ serial_putc (*s++);
+ }
+}
diff -urP u-boot.orig-20060405/cpu/arm920t/ep93xx/speed.c
u-boot.scrubbed-20060405/cpu/arm920t/ep93xx/speed.c
--- u-boot.orig-20060405/cpu/arm920t/ep93xx/speed.c 1969-12-31
19:00:00.000000000 -0500
+++ u-boot.scrubbed-20060405/cpu/arm920t/ep93xx/speed.c 2006-04-05
09:47:42.000000000 -0400
@@ -0,0 +1,83 @@
+/* vim: set ts=8 sw=8 noet:
+ *
+ * Cirrus Logic EP93xx PLL support.
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@xxxxxxxxxxxxxxxxxx>
+ *
+ * Based on the S3C24x0 speed.c, which is
+ *
+ * (C) Copyright 2001-2002
+ * Wolfgang Denk, DENX Software Engineering, <wd@xxxxxxx>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@xxxxxxxxx>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <ep93xx.h>
+
+
+#define MPLL 0
+#define UPLL 1
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static ulong get_PLLCLK(int pllreg)
+{
+ /* to be implemented */
+ return 0;
+}
+
+/* return FCLK frequency */
+/* the parameter here is to force lookup on trunk 0 or trunk 1 of the clock
tree
+ * independent from what the chip is programmed to. to just get FCLK pass in
something other then 0
+ */
+ulong get_FCLK(int trunk)
+{
+ /* to be implemented */
+ return 0;
+}
+
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+ /* to be implemented */
+ return 0;
+}
+
+ulong get_UART_PCLK(void)
+{
+ /* to be implemented */
+ return 0;
+}
+
+ulong get_TIMER_PCLK(void)
+{
+ /* to be implemented */
+ return 0;
+}
diff -urP u-boot.orig-20060405/cpu/arm920t/start.S
u-boot.scrubbed-20060405/cpu/arm920t/start.S
--- u-boot.orig-20060405/cpu/arm920t/start.S 2005-11-29 12:46:11.000000000
-0500
+++ u-boot.scrubbed-20060405/cpu/arm920t/start.S 2006-04-05
09:47:42.000000000 -0400
@@ -5,6 +5,9 @@
* Copyright (c) 2002 Alex Züpke <azu@xxxxxxxx>
* Copyright (c) 2002 Gary Jennejohn <gj@xxxxxxx>
*
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@xxxxxxxxxxxxxxxxxx>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -39,7 +42,18 @@
.globl _start
-_start: b reset
+_start:
+/* The Cirrus EP93xx internal boot ROM requires this 4-byte header for proper
+ * operation. Refer to the "Boot ROM" chapter in the User's Guide for more
+ * information. */
+#if (defined(CONFIG_EP93XX) && defined(__GNUC__) && defined(__ARMEL__))
+ .ascii "CRUS"
+#elif (defined(CONFIG_EP93XX) && defined(__GNUC__) && defined(__ARMEB__))
+ .ascii "SURC"
+#elif defined(CONFIG_EP93XX)
+#error FIXME - unable to determine EP93xx endianness
+#endif
+ b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
diff -urP u-boot.orig-20060405/include/configs/edb93xx.h
u-boot.scrubbed-20060405/include/configs/edb93xx.h
--- u-boot.orig-20060405/include/configs/edb93xx.h 1969-12-31
19:00:00.000000000 -0500
+++ u-boot.scrubbed-20060405/include/configs/edb93xx.h 2006-04-05
09:47:50.000000000 -0400
@@ -0,0 +1,308 @@
+/* vim: set ts=8 sw=8 noet: */
+/*
+ * Configuration settings for Cirrus Logic EDB93xx boards.
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@xxxxxxxxxxxxxxxxxx>
+ *
+ * Original EDB93xx port done by llandre <r&d2@xxxxxxxxxxxx>
+ *
+ * Based on the settings found in smdk2410.h, which is
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@xxxxxxxx>
+ * Gary Jennejohn <gj@xxxxxxx>
+ * David Mueller <d.mueller@xxxxxxxxx>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#if !defined(EDB93XX_H)
+#define EDB93XX_H
+
+
+/*
-----------------------------------------------------------------------------
+ * Initial environment and monitor configuration options.
+ *
+ * These should be set appropriately for your particular development
+ * environment. Refer to the README for more detailed descriptions.
+ */
+#define CONFIG_ETHADDR 08:00:3E:26:0A:5B
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.128.224
+#define CONFIG_SERVERIP 192.168.128.181
+#define CONFIG_GATEWAYIP 192.168.4.1
+
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_BOOTARGS "root=/dev/mtdblock/0
console=ttyAM0,115200 ip=::::::dhcp"
+#define CONFIG_BOOTFILE "foo.img"
+#define CONFIG_BOOTCOMMAND "bootm"
+
+
+/*
-----------------------------------------------------------------------------
+ * Do NOT touch anything below this point unless you know what you are doing!
+ */
+
+/*
-----------------------------------------------------------------------------
+ * High level configuration options
+ */
+
+/* This is an ARM920T core, in a Cirrus Logic 93xx SoC, on a Cirrus Logic
+ * EDB93xx board. Note that 'make' will set the proper CONFIG_EP93<nn> and
+ * CONFIG_EDB93<nn> symbols. */
+#define CONFIG_ARM920T
+#define CONFIG_EP93XX
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ 3686400 /* the EP9312 has 3.6864MHz input clock
*/
+
+/* Timer 3 set for 2KHz operation */
+#define CFG_HZ 2048
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+
+/* #define USE_920T_MMU 1*/
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+
+/*
-----------------------------------------------------------------------------
+ * Monitor configuration
+ *
+ * Define the set of commands supported for the various EDB93xx boards, as
+ * well as the default monitor prompt and amount of help available.
+ */
+#if defined(USE_920T_MMU)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_PING | \
+ CFG_CMD_MII)
+
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_PING | \
+ CFG_CMD_MII & \
+ ~CFG_CMD_CACHE)
+#endif /* defined(USE_920T_MMU) */
+
+#include <cmd_confdefs.h> /* Must be AFTER any CONFIG_COMMANDS */
+
+
+#if defined(CONFIG_EDB9301)
+#define CFG_PROMPT "EDB9301> "
+
+#elif defined(CONFIG_EDB9302)
+#define CFG_PROMPT "EDB9302> "
+
+#elif defined(CONFIG_EDB9307)
+#define CFG_PROMPT "EDB9307> "
+
+#elif defined(CONFIG_EDB9312)
+#define CFG_PROMPT "EDB9312> "
+
+#elif defined(CONFIG_EDB9315)
+#define CFG_PROMPT "EDB9315> "
+
+#else
+#define CFG_PROMPT "EDB93xx> "
+#endif /* defined(CONFIG_EDB93nn) */
+
+/* Enable "long" help in the monitor */
+#define CFG_LONGHELP
+
+#define CFG_CBSIZE 1024 /* Console I/O Buffer
Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer
Size */
+#define CFG_MAXARGS 16 /* max number of
command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size
*/
+
+
+#define CFG_LOAD_ADDR 0x01000000 /* default load address
*/
+
+
+/*
-----------------------------------------------------------------------------
+ * Serial port hardware configuration
+ *
+ * We default to using serial port 1 at 115200 baud.
+ * TODO: kgdb support has NOT been verified as functional.
+ */
+#define CONFIG_SERIAL1 (1)
+#define CONFIG_BAUDRATE (115200)
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#if 0
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_SER_INDEX (1)
+#define CONFIG_KGDB_BAUDRATE (115200)
+#endif
+#endif
+
+
+/*
-----------------------------------------------------------------------------
+ * Network hardware configuration
+ *
+ * We use the internal EP93xx MAC with and external MII compliant PHY.
+ * TODO: netconsole support has NOT been verified as functional.
+ */
+#if (defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
+ defined(CONFIG_EDB9307) || defined(CONFIG_EDB9312) || \
+ defined(CONFIG_EDB9315))
+#define CONFIG_DRIVER_EP93XX_MAC
+#define CONFIG_MII_SUPPRESS_PREAMBLE
+#define CONFIG_MII
+#define CONFIG_PHY_ADDR (1)
+
+#undef CONFIG_NETCONSOLE
+
+#endif /* defined(CONFIG_EDB93nn) */
+
+
+/*
-----------------------------------------------------------------------------
+ * Physical memory map
+ *
+ * The EDB9301 and EDB9302 have 1 bank of SDRAM at 0x00000000 consisting of
+ * 1x Samsung K4S561632E-TC75 256 Mbit SDRAM on a 16-bit data bus, for a total
+ * of 32 MB of SDRAM.
+ *
+ * The EDB9307, EDB9312, and EDB9315 have 1 bank of SDRAM at 0x00000000
+ * consisting of 2x Samsung K4S561632E-TC75 256 Mbit SDRAMs on a 32-bit data
+ * bus, for a total of 64 MB of SDRAM.
+ */
+#if (defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302))
+#define CONFIG_NR_DRAM_BANKS (1)
+#define PHYS_SDRAM_1 (0x00000000)
+#define PHYS_SDRAM_SIZE_1 (0x02000000)
+
+#define CFG_MEMTEST_START (0x00000000)
+#define CFG_MEMTEST_END (0x01F00000)
+
+#elif (defined(CONFIG_EDB9307) || defined(CONFIG_EDB9312) || \
+ defined(CONFIG_EDB9315))
+#define CONFIG_NR_DRAM_BANKS (1)
+#define PHYS_SDRAM_1 (0x00000000)
+#define PHYS_SDRAM_SIZE_1 (0x04000000)
+
+#define CFG_MEMTEST_START (0x00000000)
+#define CFG_MEMTEST_END (0x03F00000)
+
+#endif /* defined(CONFIG_EDB93nn) */
+
+
+/* Address in RAM to which boot parameters will be copied from the environment.
+ * This must match the kernel is expecting. */
+#define CONFIG_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
+
+
+/*
-----------------------------------------------------------------------------
+ * Run-time memory allocations
+ *
+ * The global data area size (must be > sizeof(gd_t)), stack sizes, and heap
+ * size are set using the values below.
+ */
+#define CFG_GBL_DATA_SIZE (128)
+
+#define CONFIG_STACKSIZE (128 * 1024)
+
+#if defined(CONFIG_USE_IRQ)
+#define CONFIG_STACKSIZE_IRQ (4 * 1024)
+#define CONFIG_STACKSIZE_FIQ (4 * 1024)
+#endif /* defined(CONFIG_USE_IRQ) */
+
+#define CFG_MALLOC_LEN (512 * 1024)
+
+
+/*
-----------------------------------------------------------------------------
+ * FLASH and environment organization
+ *
+ * The EDB9301 and EDB9302 have 1 bank of flash memory at 0x60000000 consisting
+ * of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus, for a total
+ * of 16 MB of CFI-compatible flash.
+ *
+ * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at 0x60000000
+ * consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit data bus,
+ * for a total of 32 MB of CFI-compatible flash.
+ *
+ * EDB9301/02 EDB9307/12/15
+ * 0x00000000 - 0x0003FFFF u-boot u-boot
+ * 0x00040000 - 0x0005FFFF environment #1 environment #1
+ * 0x00060000 - 0x0007FFFF unused environment #1 (continued)
+ * 0x00080000 - 0x0009FFFF environment #2 environment #2
+ * 0x000A0000 - 0x000BFFFF unused environment #2 (continued)
+ * 0x000C0000 - 0x000FFFFF unused unused
+ * 0x00100000 - 0x002FFFFF kernel image #1 kernel image #1
+ * 0x00300000 - 0x004FFFFF kernel image #2 kernel image #2
+ * 0x00500000 - 0x00FFFFFF JFFS2 JFFS2
+ * 0x01000000 - 0x01FFFFFF not present JFFS2 (continued)
+ */
+#if (defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302))
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS (1)
+#define CFG_MAX_FLASH_SECT (128)
+
+#define PHYS_FLASH_1 (0x60000000)
+#define CFG_FLASH_BASE (PHYS_FLASH_1)
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
+#define CFG_MONITOR_LEN (256 * 1024)
+
+#define CONFIG_ENV_OVERWRITE /* Vendor parameters are unprotected */
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_ADDR (0x60040000)
+#define CFG_ENV_ADDR_REDUND (0x60080000)
+#define CFG_ENV_SECT_SIZE (0x00020000)
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
+
+#define CFG_JFFS2_FIRST_BANK (0)
+#define CFG_JFFS2_FIRST_SECTOR (28)
+#define CFG_JFFS2_NUM_BANKS (1)
+
+#elif (defined(CONFIG_EDB9307) || defined(CONFIG_EDB9312) || \
+ defined(CONFIG_EDB9315))
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS (1)
+#define CFG_MAX_FLASH_SECT (128)
+
+#define PHYS_FLASH_1 (0x60000000)
+#define CFG_FLASH_BASE (PHYS_FLASH_1)
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
+#define CFG_MONITOR_LEN (256 * 1024)
+
+#define CONFIG_ENV_OVERWRITE /* Vendor parameters are unprotected */
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_ADDR (0x60040000)
+#define CFG_ENV_ADDR_REDUND (0x60080000)
+#define CFG_ENV_SECT_SIZE (0x00040000)
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
+
+#define CFG_JFFS2_FIRST_BANK (0)
+#define CFG_JFFS2_FIRST_SECTOR (14)
+#define CFG_JFFS2_NUM_BANKS (1)
+
+#endif /* defined(CONFIG_EDB93nn) */
+
+
+#endif /* !defined(EDB93XX_H) */
+
diff -urP u-boot.orig-20060405/include/ep93xx.h
u-boot.scrubbed-20060405/include/ep93xx.h
--- u-boot.orig-20060405/include/ep93xx.h 1969-12-31 19:00:00.000000000
-0500
+++ u-boot.scrubbed-20060405/include/ep93xx.h 2006-04-05 09:47:50.000000000
-0400
@@ -0,0 +1,1255 @@
+/* Cirrus LogicEP9312 header file
+ * From Cirrus Spec Revision 0.14
+ * Copyright 2002 2003
+ * Adam Bezanson, Network Audio Technologies, Inc.
+ * bezanson@xxxxxxxxxxxxxxxx
+ * 12/26/02
+ */
+
+/* UART 1 REGISTERS */
+#define rUART1_DR (*(volatile unsigned *)0x808c0000)
+#define rUART1_RSR (*(volatile unsigned *)0x808c0004)
+#define rUART1_LCR_H (*(volatile unsigned *)0x808c0008)
+#define rUART1_LCR_M (*(volatile unsigned *)0x808c000c)
+#define rUART1_LCR_L (*(volatile unsigned *)0x808c0010)
+#define rUART1_CR (*(volatile unsigned *)0x808c0014)
+#define rUART1_FR (*(volatile unsigned *)0x808c0018)
+#define rUART1_IIR (*(volatile unsigned *)0x808c001c)
+
+/* SYSCON Regs */
+#define SysconCLKSET1 (*(volatile unsigned *)0x80930020)
+#define SysconCLKSET1VAL 0x02a4a3d7
+#define SysconCLKSET2 (*(volatile unsigned *)0x80930024)
+#define SysconCLKSET2VAL 0x700CC317
+#define SysconDEVCFG (*(volatile unsigned *)0x80930080)
+#define SysconCHIP_ID (*(volatile unsigned *)0x80930094)
+#define SysconCFG (*(volatile unsigned *)0x8093009C)
+#define SysconSWLock (*(volatile unsigned *)0x809300C0)
+
+#define SYSCON_SW_UNCLOCK do { SysconSWLock |= 0xAA; } while(0)
+
+/* Security regs */
+#define SecurityExtensionID (*(volatile unsigned *)0x80832714)
+
+/*-----------------------------------------------------------------------------
+ * SYSCON_CLKSET1
+
*-----------------------------------------------------------------------------*/
+#define SYSCON_CLKSET1_PLL1_X2IPD_SHIFT 0
+#define SYSCON_CLKSET1_PLL1_X2IPD_MASK 0x0000001f
+#define SYSCON_CLKSET1_PLL1_X2FBD2_SHIFT 5
+#define SYSCON_CLKSET1_PLL1_X2FBD2_MASK 0x000007e0
+#define SYSCON_CLKSET1_PLL1_X1FBD1_SHIFT 11
+#define SYSCON_CLKSET1_PLL1_X1FBD1_MASK 0x0000f800
+#define SYSCON_CLKSET1_PLL1_PS_SHIFT 16
+#define SYSCON_CLKSET1_PLL1_PS_MASK 0x00030000
+#define SYSCON_CLKSET1_PCLKDIV_SHIFT 18
+#define SYSCON_CLKSET1_PCLKDIV_MASK 0x000c0000
+#define SYSCON_CLKSET1_HCLKDIV_SHIFT 20
+#define SYSCON_CLKSET1_HCLKDIV_MASK 0x00700000
+#define SYSCON_CLKSET1_nBYP1 0x00800000
+#define SYSCON_CLKSET1_SMCROM 0x01000000
+#define SYSCON_CLKSET1_FCLKDIV_SHIFT 25
+#define SYSCON_CLKSET1_FCLKDIV_MASK 0x0e000000
+
+/* Timer STUFF for interrupts.c */
+#define Timer1Load (*(volatile unsigned *)0x80810000)
+#define Timer1Value (*(volatile unsigned *)0x80810004)
+#define Timer1Control (*(volatile unsigned *)0x80810008)
+
+
+
+/* Ethernet MAC, Info Copied from Cirrus Logic Verisuite info */
+/*
+* 15.2 PCI Operational Registers
+* (The addresses shown are relative to the IO base address register)
+*/
+#define OpReg_RxCTL (*(volatile unsigned *)0x80010000) /* 4-RW Receive
Control */
+#define OpReg_TxCTL (*(volatile unsigned *)0x80010004) /* 1-RW Transmit
Control */
+#define OpReg_TestCTL (*(volatile unsigned *)0x80010008) /* 1-RW Test
Control */
+#define OpReg_MIICmd (*(volatile unsigned *)0x80010010) /* 2-RW MII(Media
Independent Intf) Command */
+#define OpReg_MIIData (*(volatile unsigned *)0x80010014) /* 2-RW MII Data */
+#define OpReg_MIISts (*(volatile unsigned *)0x80010018) /* 1-RO MII Status
*/
+
+#define OpReg_SelfCTL (*(volatile unsigned *)0x80010020) /* 1-RW Self
Control for LED interface */
+#define OpReg_IntEn (*(volatile unsigned *)0x80010024) /* 4-RW Interrupt
Enable */
+#define OpReg_IntStsP (*(volatile unsigned *)0x80010028) /* 4-RW Interrupt
Status Preserve */
+#define OpReg_IntStsC (*(volatile unsigned *)0x8001002C) /* 4-RO Interrupt
Status Clear */
+
+#define OpReg_GT (*(volatile unsigned *)0x80010040) /* 4-RW General
Timer */
+#define OpReg_FCT (*(volatile unsigned *)0x80010044) /* 4-RO Flow
Control Timer */
+#define OpReg_FCF (*(volatile unsigned *)0x80010048) /* 4-RW Flow
Control Format */
+#define OpReg_AFP (*(volatile unsigned *)0x8001004C) /* 1-RW Address
Filter Pointer */
+#define OpReg_HashTb (*(volatile unsigned *)0x80010050) /* 8-RW Logical
Address Filter (Hash Table) */
+#define OpReg_IndAd (*(volatile unsigned *)0x80010050) /* 6-RW Individual
Address, IA */
+#define OpReg_IndAd1 (*(volatile unsigned *)0x80010054) /* 6-RW Individual
Address, IA */
+
+#define OpReg_FERMask (*(volatile unsigned *)0x80010064) /* 4-RW Cardbus
Function Event Mask Register */
+
+#define OpReg_TxCollCnt (*(volatile unsigned *)0x80010070) /* 2-RO Transmit
Collision Count */
+#define OpReg_RxMissCnt (*(volatile unsigned *)0x80010074) /* 2-RO Receive
Miss Count */
+#define OpReg_RxRuntCnt (*(volatile unsigned *)0x80010078) /* 2-RO Receive
Runt Count */
+
+#define OpReg_BMCTL (*(volatile unsigned *)0x80010080) /* 2-RW Bus Master
Control */
+#define OpReg_BMSts (*(volatile unsigned *)0x80010084) /* 1-RO Bus Master
Status */
+#define OpReg_RxBCA (*(volatile unsigned *)0x80010088) /* 4-RO Receive
buffer current address */
+#define OpReg_TxBCA (*(volatile unsigned *)0x8001008C) /* 4-RO Transmit
buffer current address */
+#define OpReg_RxDBA (*(volatile unsigned *)0x80010090) /* 4-RW Receive
Descriptor Queue Base Address */
+#define OpReg_RxDBL (*(volatile unsigned *)0x80010094) /* 2-RW Receive
Descriptor Queue Base Length */
+#define OpReg_RxDCL (*(volatile unsigned *)0x80010096) /* 2-RW Receive
Descriptor Queue Current Length */
+#define OpReg_RxDCA (*(volatile unsigned *)0x80010098) /* 4-RW Receive
Descriptor Current Address */
+#define OpReg_RxDEQ (*(volatile unsigned *)0x8001009C) /* 4-RW Receive
Descriptor Enqueue */
+
+#define OpReg_RxSBA (*(volatile unsigned *)0x800100A0) /* 4-RW Receive
Status Queue Base Address */
+#define OpReg_RxSBL (*(volatile unsigned *)0x800100A4) /* 2-RW Receive
Status Queue Base Length */
+#define OpReg_RxSCL (*(volatile unsigned *)0x800100A6) /* 2-RW Receive
Status Queue Current Length */
+#define OpReg_RxSCA (*(volatile unsigned *)0x800100A8) /* 4-RW Receive
Status Current Address */
+#define OpReg_RxSEQ (*(volatile unsigned *)0x800100AC) /* 4-RW Receive
Status Enqueue */
+#define OpReg_TxDBA (*(volatile unsigned *)0x800100B0) /* 4-RW Transmit
Descriptor Queue Base Address */
+#define OpReg_TxDBL (*(volatile unsigned *)0x800100B4) /* 2-RW Transmit
Descriptor Queue Base Length */
+#define OpReg_TxDCL (*(volatile unsigned *)0x800100B6) /* 2-RW Transmit
Descriptor Queue Current Length */
+#define OpReg_TxDCA (*(volatile unsigned *)0x800100B8) /* 4-RW Transmit
Descriptor Current Address */
+#define OpReg_TxDEQ (*(volatile unsigned *)0x800100BC) /* 4-RW Transmit
Descriptor Enqueue */
+
+#define OpReg_TxSBA (*(volatile unsigned *)0x800100C0) /* 4-RW Transmit
status Queue Base Address */
+#define OpReg_TxSBL (*(volatile unsigned *)0x800100C4) /* 2-RW Transmit
Status Queue Base Length */
+#define OpReg_TxSCL (*(volatile unsigned *)0x800100C6) /* 2-RW Transmit
Status Queue Current Length */
+#define OpReg_TxSCA (*(volatile unsigned *)0x800100C8) /* 4-RW Transmit
Status Current Address */
+#define OpReg_RxBTH (*(volatile unsigned *)0x800100D0) /* 4-RW Receive
Buffer Threshold */
+#define OpReg_TxBTH (*(volatile unsigned *)0x800100D4) /* 4-RW Transmit
Buffer Threshold */
+#define OpReg_RxSTH (*(volatile unsigned *)0x800100D8) /* 4-RW Receive
Status Threshold */
+#define OpReg_TxSTH (*(volatile unsigned *)0x800100DC) /* 4-RW Transmit
Status Threshold */
+
+#define OpReg_RxDTH (*(volatile unsigned *)0x800100E0) /* 4-RW Receive
Descriptor Threshold */
+#define OpReg_TxDTH (*(volatile unsigned *)0x800100E4) /* 4-RW Transmit
Descriptor Threshold */
+#define OpReg_MaxFL (*(volatile unsigned *)0x800100E8) /* 4-RW Maximum
Frame Length */
+#define OpReg_RxHLen (*(volatile unsigned *)0x800100EC) /* 4-RW Receive
Header Length */
+
+
+/***************************************************************************/
+/***************************************************************************/
+
+/*
+* OpReg_RxCTL 0x0000 4-RW Receive Control
+*/
+#define RxCTL_PauseAccept (1L<<0x14) /* */
+#define RxCTL_RxFlowControlEn1 (1L<<0x13) /* */
+#define RxCTL_RxFlowControlEn0 (1L<<0x12) /* */
+#define RxCTL_BufferCRC (1L<<0x11) /* */
+#define RxCTL_SerRxON (1L<<0x10) /* */
+
+#define RxCTL_RuntCRCA (1L<<0x0D) /* */
+#define RxCTL_RuntA (1L<<0x0C) /* */
+#define RxCTL_PromiscuousA (1L<<0x0B) /* */
+#define RxCTL_BroadcastA (1L<<0x0A) /* */
+#define RxCTL_MulticastA (1L<<0x09) /* */
+#define RxCTL_IAHashA (1L<<0x08) /* */
+
+#define RxCTL_IndividualAccept3 (1L<<0x03) /* */
+#define RxCTL_IndividualAccept2 (1L<<0x02) /* */
+#define RxCTL_IndividualAccept1 (1L<<0x01) /* */
+#define RxCTL_IndividualAccept0 (1L<<0x00) /* */
+
+
+/*
+* OpReg_TxCTL 0x0004 1-RW Transmit Control
+*/
+#define TxCTL_2PartDefDis (1<<0x07) /* */
+#define TxCTL_ModBackOffE (1<<0x06) /* */
+#define TxCTL_InhibitCRC (1<<0x05) /* */
+#define TxCTL_TxPadDis (1<<0x04) /* */
+#define TxCTL_OneColl (1<<0x03) /* */
+#define TxCTL_SendPause (1<<0x02) /* */
+#define TxCTL_PauseBusy (1<<0x01) /* */
+#define TxCTL_SerTxON (1<<0x00) /* */
+
+
+/*
+* OpReg_TestCTL 0x0008 1-RW Test Control
+*/
+#define TestCTL_MACFast (1<<0x07) /* */
+#define TestCTL_MACFDX (1<<0x06) /* */
+#define TestCTL_DisableBackoff (1<<0x05) /* */
+#define TestCTL_MIIFast (1<<0x04) /* */
+
+
+/*
+* OpReg_MIICmd 0x0010 2-RW MII(Media Independent Intf) Command
+*/
+#define MIICmd_RegAd_Mask (0x001F) /* */
+#define MIICmd_PhyAd_Mask (0x03E0) /* */
+#define MIICmd_Opcode_Mask (0xC000) /* */
+
+
+/** QQQQQQQ */
+#define MIICmd_PhyAd_8950 (0x0000) /* Address the 8950
Phy */
+#define MIICmd_Opcode_Read (0x8000) /* Read register */
+#define MIICmd_Opcode_Write (0x4000) /* Write register */
+
+
+
+/*
+* OpReg_MIIData 0x0014 2-RW MII Data
+*/
+
+/* this place left intentionally blank */
+
+/*
+* OpReg_MIISts 0x0018 1-RO MII Status
+*/
+#define MIISts_Busy (1<<0x00) /* */
+
+/*
+* OpReg_SelfCTL 0x0020 1-RW Self Control for LED interface
+*/
+#define SelfCTL_WakeupViaLAN (1<<0x07) /* */
+
+#define SelfCTL_GPO (1<<0x05) /* */
+#define SelfCTL_PoweredUpWakeupEn (1<<0x04) /* */
+#define SelfCTL_PoweredDownWakeupEn (1<<0x03) /* */
+#define SelfCTL_MIILoopback (1<<0x02) /* */
+
+#define SelfCTL_RESET (1<<0x00) /* */
+
+
+/*
+* OpReg_IntEn 0x0024 4-RW Interrupt Enable
+*/
+#define IntEn_WakeupViaLANiE (1L<<0x1e) /* */
+#define IntEn_RxMissiE (1L<<0x1d) /* */
+#define IntEn_RxBuffersiE (1L<<0x1c) /* */
+#define IntEn_RxStsQiE (1L<<0x1b) /* */
+#define IntEn_TxLenErriE (1L<<0x1a) /* */
+#define IntEn_EndofChainiE (1L<<0x19) /* */
+#define IntEn_TxUnderrunHaltiE (1L<<0x18) /* */
+
+#define IntEn_MissOviE (1L<<0x12) /* */
+#define IntEn_TxCollOviE (1L<<0x11) /* */
+#define IntEn_RxRuntOviE (1L<<0x10) /* */
+
+#define IntEn_MIIStsiE (1L<<0x0c) /* */
+#define IntEn_PhyStsiE (1L<<0x0b) /* */
+#define IntEn_TimeoutiE (1L<<0x0a) /* */
+#define IntEn_SWintiE (1L<<0x08) /* */
+
+#define IntEn_TxStsQiE (1L<<0x03) /* */
+#define IntEn_RxEOFiE (1L<<0x02) /* */
+#define IntEn_RxEOBiE (1L<<0x01) /* */
+#define IntEn_RxHdriE (1L<<0x00) /* */
+
+
+/*
+* OpReg_IntStsP 0x0028 4-RW Interrupt Status Preserve
+* OpReg_IntStsC 0x002C 4-RO Interrupt Status Clear
+*/
+#define IntSts_WakeupViaLAN (1L<<0x1e) /* */
+#define IntSts_RxMiss (1L<<0x1d) /* */
+#define IntSts_RxBuffers (1L<<0x1c) /* */
+#define IntSts_RxStsSEQ (1L<<0x1b) /* */
+#define IntSts_TxLenErr (1L<<0x1a) /* */
+#define IntSts_EndofChain (1L<<0x19) /* */
+#define IntSts_TxUnderrunHalt (1L<<0x18) /* */
+
+#define IntSts_MissOv (1L<<0x12) /* */
+#define IntSts_TxCollOv (1L<<0x11) /* */
+#define IntSts_RxRuntOv (1L<<0x10) /* */
+
+#define IntSts_MIISts (1L<<0x0c) /* */
+#define IntSts_PhySts (1L<<0x0b) /* */
+#define IntSts_Timeout (1L<<0x0a) /* */
+#define IntSts_SWint (1L<<0x08) /* */
+
+#define IntSts_Other (1L<<0x04) /* */
+#define IntSts_TxStsQ (1L<<0x03) /* */
+#define IntSts_RxStsQ (1L<<0x02) /* */
+
+
+
+/*
+* OpReg_GT 0x0040 4-RW General Timer
+*/
+#define GT_Count_Mask (0xFFFF0000) /* */
+#define GT_Period_Mask (0x0000FFFF) /* */
+
+
+/*
+* OpReg_FCT 0x0044 4-RO Flow Control Timer
+*/
+#define FCT_Timer_Mask (0x00FFFFFF) /* */
+
+
+/*
+* OpReg_FCF 0x0048 4-RW Flow Control Format
+*/
+#define FCF_MACCTLType_Mask (0xFFFF0000) /* */
+#define FCF_TxPauseTime_Mask (0x0000FFFF) /* */
+
+
+/*
+* OpReg_AFP 0x004C 1-RW Address Filter Pointer
+*/
+#define AFP_Mask (0x07) /* */
+
+#define AFP_IAPrimary (0x00) /* primary IA for Wakeup, Tx
pause and Rx pause frames */
+#define AFP_IASecondary1 (0x01) /* secondary IA for Rx pause
frames */
+#define AFP_IASecondary2 (0x02) /* secondary IA for qualifying
Rx frames */
+#define AFP_IASecondary3 (0x03) /* secondary IA for qualifying
Rx frames */
+
+#define AFP_Tx (0x06) /* destination address for Tx
*/
+#define AFP_Hash (0x07) /* hash table */
+
+
+/*
+* OpReg_HashTb 0x0050 8-RW Logical Address Filter (Hash Table)
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_IndAd 0x0050 6-RW Individual Address, IA
+*/
+
+/* this place left intentionally blank */
+
+
+
+/*
+* OpReg_FERMask 0x0064 4-RW Cardbus Function Event Mask Register
+*/
+#define FERMask_Interrupt (1L<<0x0F) /* */
+
+
+/*
+* OpReg_TxCollCnt 0x0070 2-RO Transmit Collision Count
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_RxMissCnt 0x0074 2-RO Receive Miss Count
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_RxRuntCnt 0x0078 2-RO Receive Runt Count
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_BMCTL 0x0080 2-RW Bus Master Control
+*/
+#define BMCTL_ManualTrans (1<<0x0d) /* */
+#define BMCTL_TimedTrans (1<<0x0c) /* */
+#define BMCTL_UnderrunHalt (1<<0x0b) /* */
+#define BMCTL_TxChRes (1<<0x0a) /* */
+#define BMCTL_TxDis (1<<0x09) /* */
+#define BMCTL_TxEn (1<<0x08) /* */
+
+#define BMCTL_EnHeader2 (1<<0x06) /* */
+#define BMCTL_EnHeader1 (1<<0x05) /* */
+#define BMCTL_EnEOB (1<<0x04) /* */
+
+#define BMCTL_RxChRes (1<<0x02) /* */
+#define BMCTL_RxDis (1<<0x01) /* */
+#define BMCTL_RxEn (1<<0x00) /* */
+
+
+/*
+* OpReg_BMSts 0x0084 1-RO Bus Master Status
+*/
+#define BMSts_TxAct (1<<0x07) /* */
+
+#define BMSts_TransPending (1<<0x04) /* */
+#define BMSts_RxAct (1<<0x03) /* */
+
+#define BMSts_QueueID_Mask (0x07) /* */
+
+#define BMSts_QueueID_RxData (0x00) /* */
+#define BMSts_QueueID_TxData (0x01) /* */
+#define BMSts_QueueID_RxSts (0x02) /* */
+#define BMSts_QueueID_TxSts (0x03) /* */
+#define BMSts_QueueID_RxDesc (0x04) /* */
+#define BMSts_QueueID_TxDesc (0x05) /* */
+
+
+
+/*
+* OpReg_RxBCA 0x0088 4-RO Receive buffer current address
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_TxBCA 0x008C 4-RO Transmit buffer current address
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_RxDBA 0x0090 4-RW Receive Descriptor Queue Base Address
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_RxDBL 0x0094 2-RW Receive Descriptor Queue Base Length
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_RxDCL 0x0096 2-RW Receive Descriptor Queue Current Length
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_RxDCA 0x0098 4-RW Receive Descriptor Current Address
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_RxDEQ 0x009C 4-RW Receive Descriptor Enqueue
+*/
+#define RxDEQ_Inc_Mask (0x000000FF) /* */
+#define RxDEQ_Value_Mask (0xFFFF0000) /* for reading */
+
+
+/*
+* OpReg_RxSBA 0x00A0 4-RW Receive Status Queue Base Address
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_RxSBL 0x00A4 2-RW Receive Status Queue Base Length
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_RxSCL 0x00A6 2-RW Receive Status Queue Current Length
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_RxSCA 0x00A8 4-RW Receive Status Current Address
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_RxSEQ 0x00AC 4-RW Receive Status Enqueue
+*/
+#define RxSEQ_Inc_Mask (0x000000FF) /* */
+#define RxSEQ_Value_Mask (0xFFFF0000) /* for reading */
+
+
+/*
+* OpReg_TxDBA 0x00B0 4-RW Transmit Descriptor Queue Base Address
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_TxDBL 0x00B4 2-RW Transmit Descriptor Queue Base Length
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_TxDCL 0x00B6 2-RW Transmit Descriptor Queue Current Length
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_TxDCA 0x00B8 4-RW Transmit Descriptor Current Address
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_TxDEQ 0x00BC 4-RW Transmit Descriptor Enqueue
+*/
+#define TxDEQ_Inc_Mask (0x000000FF) /* */
+#define TxDEQ_Value_Mask (0xFFFF0000) /* for reading */
+
+
+/*
+* OpReg_TxSBA 0x00C0 4-RW Transmit status Queue Base Address
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_TxSBL 0x00C4 2-RW Transmit Status Queue Base Length
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_TxSCL 0x00C6 2-RW Transmit Status Queue Current Length
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_TxSCA 0x00C8 4-RW Transmit Status Current Address
+*/
+
+/* this place left intentionally blank */
+
+
+/*
+* OpReg_RxBTH 0x00D0 4-RW Receive Buffer Threshold
+*/
+#define RxBTH_SoftTh_Mask (0x000003FF) /* */
+#define RxBTH_HardTh_Mask (0x03FF0000) /* */
+
+
+/*
+* OpReg_TxBTH 0x00D4 4-RW Transmit Buffer Threshold
+*/
+#define TxBTH_SoftTh_Mask (0x000003FF) /* */
+#define TxBTH_HardTh_Mask (0x03FF0000) /* */
+
+
+/*
+* OpReg_RxSTH 0x00D8 4-RW Receive Status Threshold
+*/
+#define RxSTH_SoftTh_Mask (0x0000003F) /* */
+#define RxSTH_HardTh_Mask (0x003F0000) /* */
+
+
+/*
+* OpReg_TxSTH 0x00DC 4-RW Transmit Status Threshold
+*/
+#define TxSTH_SoftTh_Mask (0x0000003F) /* */
+#define TxSTH_HardTh_Mask (0x003F0000) /* */
+
+
+/*
+* OpReg_RxDTH 0x00E0 4-RW Receive Descriptor Threshold
+*/
+#define RxDTH_SoftTh_Mask (0x0000003F) /* */
+#define RxDTH_HardTh_Mask (0x003F0000) /* */
+
+
+/*
+* OpReg_TxDTH 0x00E4 4-RW Transmit Descriptor Threshold
+*/
+#define TxDTH_SoftTh_Mask (0x0000003F) /* */
+#define TxDTH_HardTh_Mask (0x003F0000) /* */
+
+
+/*
+* OpReg_MaxFL 0x00E8 4-RW Maximum Frame Length
+*/
+#define MaxFL_TxStartTh_Mask (0x000007FF) /* */
+#define MaxFL_FrameLen_Mask (0x07FF0000) /* */
+
+/*
+* OpReg_RxHLen 0x00EC 4-RW Receive Header Length
+*/
+#define RxHLen_1_Mask (0x000007FF) /* */
+#define RxHLen_2_Mask (0x07FF0000) /* */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+/* UART 3 REGISTERS */
+#define rUART3_DR (*(volatile unsigned *)0x808e0000)
+#define rUART3_RSR (*(volatile unsigned *)0x808e0004)
+#define rUART3_LCR_H (*(volatile unsigned *)0x808e0008)
+#define rUART3_LCR_M (*(volatile unsigned *)0x808e000c)
+#define rUART3_LCR_L (*(volatile unsigned *)0x808e0010)
+#define rUART3_CR (*(volatile unsigned *)0x808e0014)
+#define rUART3_FR (*(volatile unsigned *)0x808e0018)
+#define rUART3_IIR (*(volatile unsigned *)0x808e001c)
+
+/* Timer STUFF for interrupts.c */
+/* These names match what was in interrupts.c already */
+#define rTCON (*(volatile unsigned *)0x80810048)
+#define rTCNTB4 (*(volatile unsigned *)0x80810040)
+#define rTCNTO4 (*(volatile unsigned *)0x80810044)
+
+/* SYSCON REGS */
+#define PLLCFG0 (*(volatile unsigned *)0x80930004)
+#define PLLCFG1 (*(volatile unsigned *)0x80930008)
+#define PLLIDIV (*(volatile unsigned *)0x8093000c)
+#define FHDIV (*(volatile unsigned *)0x80930010)
+#define UARTDIV (*(volatile unsigned *)0x80930024)
+#define WATCHDIV (*(volatile unsigned *)0x80930030)
+
+/* Stuff for memsetup.S */
+#define RemapReg 0x80820020
+#define WatchDog 0x80940000
+#define DogDeath 0x0000AA55
+#define MiniB_LED 0x80850000
+#define PLL_STABILIZE_CNT 0x0280
+#define SYSCON_BASE 0x80930000
+#define R_RSTCR 0x0
+#define R_PLL0CFG 0x4
+#define R_PLL1CFG 0x8
+#define R_PLLIDIV 0xc
+#define R_FHDIV 0x10
+#define R_VIDDIV 0x14
+#define R_USBDIV 0x18
+#define R_IRDADIV 0x1c
+#define R_I2SDIV 0x20
+#define R_UARTDIV 0x24
+#define R_SPIDIV 0x28
+#define R_KTDIV 0x2C
+#define R_WATCHDIV 0x30
+#define R_CHIP_ID 0x34
+#define R_TSTCR 0x38
+#define R_SYSCONF 0x3C
+#define R_LOCK 0x40
+#define R_TXDIV 0x44
+#define V_RSTCR 0x00040000
+#define V_PLL0CFG 0x10809064
+#define V_PLL1CFG 0x56809064
+#define V_PLLIDIV 0x00008060
+#define V_FHDIV 0x001c800a
+#define V_VIDDIV 0x00148005
+#define V_USBDIV 0x00008004
+#define V_IRDADIV 0x800a8004
+#define V_I2SDIV 0x800f803c
+#define V_UARTDIV 0xf0008019
+#define V_SPIDIV 0xc0008032
+#define V_KTDIV 0x20018004
+#define V_WATCHDIV 0x80048024
+#define SDRAM_BASE 0x80060000
+#define CFG0 0x00
+#define CFG1 0x04
+#define CFG2 0x08
+#define CFG3 0x0C
+#define Cfg0Data 0x00A4AAAA
+#define ModeData 0x00022000
+
+/* Ethernet MAC */
+#define SelfCTL (*(volatile unsigned *)0x80010020)
+#define RxCTL (*(volatile unsigned *)0x80010000)
+#define TxCTL (*(volatile unsigned *)0x80010004)
+#define AFP (*(volatile unsigned *)0x8001004c)
+#define IndAD0 (*(volatile unsigned *)0x80010050)
+#define IndAD1 (*(volatile unsigned *)0x80010052)
+#define IndAD2 (*(volatile unsigned *)0x80010054)
+
+
+
+
+/* Some other (redundant) stuff needed by eCos-derived code */
+
+/* System control registers */
+#define EP9312_SYSCON 0x80930000
+#define EP9312_SYSCON_LOCK 0x00c0
+
+/* Clock control registers */
+#define EP9312_CLKSET1 (EP9312_SYSCON + 0x0020)
+#define EP9312_CLKSET1_NBYP 0x00800000
+#define EP9312_CLKSET1_HCLKDIV_MASK 0x00700000
+#define EP9312_CLKSET1_HCLKDIV_SHIFT 20
+#define EP9312_CLKSET1_FCLKDIV_MASK 0x0e000000
+#define EP9312_CLKSET1_FCLKDIV_SHIFT 25
+#define EP9312_CLKSET1_PCLKDIV_MASK 0x000c0000
+#define EP9312_CLKSET1_PCLKDIV_SHIFT 18
+
+#define EP9312_CLKSET2 (EP9312_SYSCON + 0x0024)
+#define EP9312_CLKSET2_PLL2_EN 0x00000001
+#define EP9312_CLKSET2_PLL2EXCLKSEL 0x00000002
+#define EP9312_CLKSET2_PLL2_P_MASK 0x0000007C
+#define EP9312_CLKSET2_PLL2_P_SHIFT 2
+#define EP9312_CLKSET2_PLL2_M2_MASK 0x00000F80
+#define EP9312_CLKSET2_PLL2_M2_SHIFT 7
+#define EP9312_CLKSET2_PLL2_M1_MASK 0x0001F000
+#define EP9312_CLKSET2_PLL2_M1 12
+#define EP9312_CLKSET2_PLL2_PS_MASK 0x000C0000
+#define EP9312_CLKSET2_PLL2_PS_SHIFT 18
+#define EP9312_CLKSET2_USBDIV_MASK 0xF0000000
+#define EP9312_CLKSET2_USBDIV_SHIFT 28
+
+#define EP9312_PWRCNT (EP9312_SYSCON + 0x0004)
+#define EP9312_PWRCNT_UARTBAUD 0x20000000
+
+#define EP9312_DEVCFG (EP9312_SYSCON + 0x0080)
+#define EP9312_DEVCFG_U1EN 0x00040000
+#define EP9312_DEVCFG_U2EN 0x00100000
+#define EP9312_DEVCFG_U3EN 0x01000000
+#define EP9312_DEVCFG_SWRST 0x80000000 /* 1->0 in this bit resets
board */
+
+/* WATCHDOG */
+#define EP9312_WATCHDOG 0x80940000
+
+/* UARTs */
+#define EP9312_UART_DATA 0x0000 /* Data/FIFO register */
+
+#define EP9312_UART_SR 0x0004 /* Status register */
+#define EP9312_UART_SR_FE 0x0001 /* Framing error */
+#define EP9312_UART_SR_PE 0x0002 /* Parity error */
+#define EP9312_UART_SR_BE 0x0004 /* Break error */
+#define EP9312_UART_SR_OE 0x0008 /* Overrun */
+
+#define EP9312_UART_LCR_H 0x0008 /* Control register High */
+#define EP9312_UART_LCR_H_BRK 0x0001 /* Send break */
+#define EP9312_UART_LCR_H_PEN 0x0002 /* Enable parity */
+#define EP9312_UART_LCR_H_EPS 0x0004 /* Odd/Even parity */
+#define EP9312_UART_LCR_H_STP2 0x0008 /* One/Two stop bits */
+#define EP9312_UART_LCR_H_FE 0x0010 /* Enable FIFO */
+#define EP9312_UART_LCR_H_WLEN5 0x0000 /* Word length - 5 bits */
+#define EP9312_UART_LCR_H_WLEN6 0x0020 /* Word length - 6 bits */
+#define EP9312_UART_LCR_H_WLEN7 0x0040 /* Word length - 7 bits */
+#define EP9312_UART_LCR_H_WLEN8 0x0060 /* Word length - 8 bits */
+
+#define EP9312_UART_LCR_M 0x000C /* Baud rate 8..15 */
+#define EP9312_UART_LCR_L 0x0010 /* Baud rate 0..7 */
+
+#define EP9312_UART_CR 0x0014 /* Control register */
+#define EP9312_UART_CR_UARTE 0x0001 /* Enable uart */
+#define EP9312_UART_CR_RIE 0x0010 /* Enable Rx interrupt */
+#define EP9312_UART_CR_TIE 0x0020 /* Enable Tx interrupt */
+#define EP9312_UART_CR_RTIE 0x0040 /* Enable Rx timeout interrupt */
+#define EP9312_UART_CR_LBE 0x0080 /* Loopback mode */
+
+#define EP9312_UART_FR 0x0018 /* Flags register */
+#define EP9312_UART_FR_CTS 0x0001 /* Clear-to-send status */
+#define EP9312_UART_FR_DSR 0x0002 /* Data-set-ready status */
+#define EP9312_UART_FR_DCD 0x0004 /* Data-carrier-detect status */
+#define EP9312_UART_FR_BUSY 0x0008 /* Transmitter busy */
+#define EP9312_UART_FR_RXFE 0x0010 /* Receive FIFO empty */
+#define EP9312_UART_FR_TXFF 0x0020 /* Transmit FIFO full */
+#define EP9312_UART_FR_RXFF 0x0040 /* Receive FIFO full */
+#define EP9312_UART_FR_TXFE 0x0080 /* Transmit FIFO empty */
+
+#define EP9312_UARTIIR 0x001C /* Interrupt status */
+#define EP9312_UARTIIR_MS 0x0001 /* Modem status interrupt */
+#define EP9312_UARTIIR_RIS 0x0002 /* Rx interrupt */
+#define EP9312_UARTIIR_TIS 0x0004 /* Tx interrupt */
+#define EP9312_UARTIIR_RTIS 0x0008 /* Rx timeout interrupt */
+
+#define EP9312_UART_MCR 0x0100 /* Modem control */
+
+#define EP9312_UART1 0x808C0000
+#define EP9312_UART2 0x808D0000
+#define EP9312_UART3 0x808E0000
+
+/* LED interface - LED0 is green, LED1 is red */
+#define EP9312_LED_DATA 0x80840020
+#define EP9312_LED_GREEN_ON 0x0001
+#define EP9312_LED_RED_ON 0x0002
+
+#define EP9312_LED_DDR 0x80840024
+#define EP9312_LED_GREEN_ENABLE 0x0001
+#define EP9312_LED_RED_ENABLE 0x0002
+
+/* Timers */
+#define EP9312_TIMERS 0x80810000
+#define EP9312_TIMERS_DEBUG_LO (EP9312_TIMERS+0x0060)
+#define EP9312_TIMERS_DEBUG_HI (EP9312_TIMERS+0x0064)
+#define EP9312_TIMERS_DEBUG_HI_RESET 0x00000000
+#define EP9312_TIMERS_DEBUG_HI_START 0x00000100
+
+/* Ethernet controller */
+#define EP9312_MAC 0x80010000
+
+#define EP9312_SDRAMCTRL 0x80060000
+
+#define EP9312_SDRAMCTRL_DEVCFG_0 0x0010
+#define EP9312_SDRAMCTRL_DEVCFG_1 0x0014
+#define EP9312_SDRAMCTRL_DEVCFG_2 0x0018
+#define EP9312_SDRAMCTRL_DEVCFG_3 0x001c
+#define EP9312_SDRAMCTRL_DEVCFG_AUTOPRE 0x01000000
+
+#define EP9312_SDRAM_PHYS_BASE 0x00000000
+
+
+/*
-----------------------------------------------------------------------------
+ * The NEW stuff...
+ */
+/* vim: set ts=8 sw=8 noet:
+ *
+ * Cirrus Logic EP93xx register definitions.
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@xxxxxxxxxxxxxxxxxx>
+ *
+ * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
+ *
+ * Copyright (C) 2004 Ray Lehtiniemi
+ * Copyright (C) 2003 Cirrus Logic, Inc
+ * Copyright (C) 1999 ARM Limited.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define ep93xx_reg32(x) (*(volatile unsigned long *)(x))
+#define ep93xx_reg16(x) (*(volatile unsigned short
*)(x))
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x80000000 - 0x8000FFFF: DMA
+ */
+#define DMA_OFFSET (0x000000)
+#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET)
+
+#define DMAMP_TX_0_CONTROL ep93xx_reg32(DMA_BASE + 0x0000)
+#define DMAMP_TX_0_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0004)
+#define DMAMP_TX_0_PPALLOC ep93xx_reg32(DMA_BASE + 0x0008)
+#define DMAMP_TX_0_STATUS ep93xx_reg32(DMA_BASE + 0x000C)
+#define DMAMP_TX_0_REMAIN ep93xx_reg32(DMA_BASE + 0x0014)
+#define DMAMP_TX_0_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x0020)
+#define DMAMP_TX_0_BASE0 ep93xx_reg32(DMA_BASE + 0x0024)
+#define DMAMP_TX_0_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0028)
+#define DMAMP_TX_0_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x0030)
+#define DMAMP_TX_0_BASE1 ep93xx_reg32(DMA_BASE + 0x0034)
+#define DMAMP_TX_0_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0038)
+
+#define DMAMP_RX_1_CONTROL ep93xx_reg32(DMA_BASE + 0x0040)
+#define DMAMP_RX_1_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0044)
+#define DMAMP_RX_1_PPALLOC ep93xx_reg32(DMA_BASE + 0x0048)
+#define DMAMP_RX_1_STATUS ep93xx_reg32(DMA_BASE + 0x004C)
+#define DMAMP_RX_1_REMAIN ep93xx_reg32(DMA_BASE + 0x0054)
+#define DMAMP_RX_1_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x0060)
+#define DMAMP_RX_1_BASE0 ep93xx_reg32(DMA_BASE + 0x0064)
+#define DMAMP_RX_1_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0068)
+#define DMAMP_RX_1_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x0070)
+#define DMAMP_RX_1_BASE1 ep93xx_reg32(DMA_BASE + 0x0074)
+#define DMAMP_RX_1_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0078)
+
+#define DMAMP_TX_2_CONTROL ep93xx_reg32(DMA_BASE + 0x0080)
+#define DMAMP_TX_2_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0084)
+#define DMAMP_TX_2_PPALLOC ep93xx_reg32(DMA_BASE + 0x0088)
+#define DMAMP_TX_2_STATUS ep93xx_reg32(DMA_BASE + 0x008C)
+#define DMAMP_TX_2_REMAIN ep93xx_reg32(DMA_BASE + 0x0094)
+#define DMAMP_TX_2_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x00A0)
+#define DMAMP_TX_2_BASE0 ep93xx_reg32(DMA_BASE + 0x00A4)
+#define DMAMP_TX_2_CURRENT0 ep93xx_reg32(DMA_BASE + 0x00A8)
+#define DMAMP_TX_2_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x00B0)
+#define DMAMP_TX_2_BASE1 ep93xx_reg32(DMA_BASE + 0x00B4)
+#define DMAMP_TX_2_CURRENT1 ep93xx_reg32(DMA_BASE + 0x00B8)
+
+#define DMAMP_RX_3_CONTROL ep93xx_reg32(DMA_BASE + 0x00C0)
+#define DMAMP_RX_3_INTERRUPT ep93xx_reg32(DMA_BASE + 0x00C4)
+#define DMAMP_RX_3_PPALLOC ep93xx_reg32(DMA_BASE + 0x00C8)
+#define DMAMP_RX_3_STATUS ep93xx_reg32(DMA_BASE + 0x00CC)
+#define DMAMP_RX_3_REMAIN ep93xx_reg32(DMA_BASE + 0x00D4)
+#define DMAMP_RX_3_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x00E0)
+#define DMAMP_RX_3_BASE0 ep93xx_reg32(DMA_BASE + 0x00E4)
+#define DMAMP_RX_3_CURRENT0 ep93xx_reg32(DMA_BASE + 0x00E8)
+#define DMAMP_RX_3_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x00F0)
+#define DMAMP_RX_3_BASE1 ep93xx_reg32(DMA_BASE + 0x00F4)
+#define DMAMP_RX_3_CURRENT1 ep93xx_reg32(DMA_BASE + 0x00F8)
+
+#define DMAMM_0_CONTROL ep93xx_reg32(DMA_BASE + 0x0100)
+#define DMAMM_0_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0104)
+#define DMAMM_0_STATUS ep93xx_reg32(DMA_BASE + 0x010C)
+#define DMAMM_0_BCR0 ep93xx_reg32(DMA_BASE + 0x0110)
+#define DMAMM_0_BCR1 ep93xx_reg32(DMA_BASE + 0x0114)
+#define DMAMM_0_SAR_BASE0 ep93xx_reg32(DMA_BASE + 0x0118)
+#define DMAMM_0_SAR_BASE1 ep93xx_reg32(DMA_BASE + 0x011C)
+#define DMAMM_0_SAR_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0124)
+#define DMAMM_0_SAR_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0128)
+#define DMAMM_0_DAR_BASE0 ep93xx_reg32(DMA_BASE + 0x012C)
+#define DMAMM_0_DAR_BASE1 ep93xx_reg32(DMA_BASE + 0x0130)
+#define DMAMM_0_DAR_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0134)
+#define DMAMM_0_DAR_CURRENT1 ep93xx_reg32(DMA_BASE + 0x013C)
+
+#define DMAMM_1_CONTROL ep93xx_reg32(DMA_BASE + 0x0140)
+#define DMAMM_1_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0144)
+#define DMAMM_1_STATUS ep93xx_reg32(DMA_BASE + 0x014C)
+#define DMAMM_1_BCR0 ep93xx_reg32(DMA_BASE + 0x0150)
+#define DMAMM_1_BCR1 ep93xx_reg32(DMA_BASE + 0x0154)
+#define DMAMM_1_SAR_BASE0 ep93xx_reg32(DMA_BASE + 0x0158)
+#define DMAMM_1_SAR_BASE1 ep93xx_reg32(DMA_BASE + 0x015C)
+#define DMAMM_1_SAR_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0164)
+#define DMAMM_1_SAR_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0168)
+#define DMAMM_1_DAR_BASE0 ep93xx_reg32(DMA_BASE + 0x016C)
+#define DMAMM_1_DAR_BASE1 ep93xx_reg32(DMA_BASE + 0x0170)
+#define DMAMM_1_DAR_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0174)
+#define DMAMM_1_DAR_CURRENT1 ep93xx_reg32(DMA_BASE + 0x017C)
+
+#define DMAMP_RX_5_CONTROL ep93xx_reg32(DMA_BASE + 0x0200)
+#define DMAMP_RX_5_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0204)
+#define DMAMP_RX_5_PPALLOC ep93xx_reg32(DMA_BASE + 0x0208)
+#define DMAMP_RX_5_STATUS ep93xx_reg32(DMA_BASE + 0x020C)
+#define DMAMP_RX_5_REMAIN ep93xx_reg32(DMA_BASE + 0x0214)
+#define DMAMP_RX_5_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x0220)
+#define DMAMP_RX_5_BASE0 ep93xx_reg32(DMA_BASE + 0x0224)
+#define DMAMP_RX_5_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0228)
+#define DMAMP_RX_5_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x0230)
+#define DMAMP_RX_5_BASE1 ep93xx_reg32(DMA_BASE + 0x0234)
+#define DMAMP_RX_5_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0238)
+
+#define DMAMP_TX_4_CONTROL ep93xx_reg32(DMA_BASE + 0x0240)
+#define DMAMP_TX_4_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0244)
+#define DMAMP_TX_4_PPALLOC ep93xx_reg32(DMA_BASE + 0x0248)
+#define DMAMP_TX_4_STATUS ep93xx_reg32(DMA_BASE + 0x024C)
+#define DMAMP_TX_4_REMAIN ep93xx_reg32(DMA_BASE + 0x0254)
+#define DMAMP_TX_4_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x0260)
+#define DMAMP_TX_4_BASE0 ep93xx_reg32(DMA_BASE + 0x0264)
+#define DMAMP_TX_4_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0268)
+#define DMAMP_TX_4_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x0270)
+#define DMAMP_TX_4_BASE1 ep93xx_reg32(DMA_BASE + 0x0274)
+#define DMAMP_TX_4_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0278)
+
+#define DMAMP_RX_7_CONTROL ep93xx_reg32(DMA_BASE + 0x0280)
+#define DMAMP_RX_7_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0284)
+#define DMAMP_RX_7_PPALLOC ep93xx_reg32(DMA_BASE + 0x0288)
+#define DMAMP_RX_7_STATUS ep93xx_reg32(DMA_BASE + 0x028C)
+#define DMAMP_RX_7_REMAIN ep93xx_reg32(DMA_BASE + 0x0294)
+#define DMAMP_RX_7_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x02A0)
+#define DMAMP_RX_7_BASE0 ep93xx_reg32(DMA_BASE + 0x02A4)
+#define DMAMP_RX_7_CURRENT0 ep93xx_reg32(DMA_BASE + 0x02A8)
+#define DMAMP_RX_7_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x02B0)
+#define DMAMP_RX_7_BASE1 ep93xx_reg32(DMA_BASE + 0x02B4)
+#define DMAMP_RX_7_CURRENT1 ep93xx_reg32(DMA_BASE + 0x02B8)
+
+#define DMAMP_TX_6_CONTROL ep93xx_reg32(DMA_BASE + 0x02C0)
+#define DMAMP_TX_6_INTERRUPT ep93xx_reg32(DMA_BASE + 0x02C4)
+#define DMAMP_TX_6_PPALLOC ep93xx_reg32(DMA_BASE + 0x02C8)
+#define DMAMP_TX_6_STATUS ep93xx_reg32(DMA_BASE + 0x02CC)
+#define DMAMP_TX_6_REMAIN ep93xx_reg32(DMA_BASE + 0x02D4)
+#define DMAMP_TX_6_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x02E0)
+#define DMAMP_TX_6_BASE0 ep93xx_reg32(DMA_BASE + 0x02E4)
+#define DMAMP_TX_6_CURRENT0 ep93xx_reg32(DMA_BASE + 0x02E8)
+#define DMAMP_TX_6_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x02F0)
+#define DMAMP_TX_6_BASE1 ep93xx_reg32(DMA_BASE + 0x02F4)
+#define DMAMP_TX_6_CURRENT1 ep93xx_reg32(DMA_BASE + 0x02F8)
+
+#define DMAMP_RX_9_CONTROL ep93xx_reg32(DMA_BASE + 0x0300)
+#define DMAMP_RX_9_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0304)
+#define DMAMP_RX_9_PPALLOC ep93xx_reg32(DMA_BASE + 0x0308)
+#define DMAMP_RX_9_STATUS ep93xx_reg32(DMA_BASE + 0x030C)
+#define DMAMP_RX_9_REMAIN ep93xx_reg32(DMA_BASE + 0x0314)
+#define DMAMP_RX_9_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x0320)
+#define DMAMP_RX_9_BASE0 ep93xx_reg32(DMA_BASE + 0x0324)
+#define DMAMP_RX_9_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0328)
+#define DMAMP_RX_9_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x0330)
+#define DMAMP_RX_9_BASE1 ep93xx_reg32(DMA_BASE + 0x0334)
+#define DMAMP_RX_9_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0338)
+
+#define DMAMP_TX_8_CONTROL ep93xx_reg32(DMA_BASE + 0x0340)
+#define DMAMP_TX_8_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0344)
+#define DMAMP_TX_8_PPALLOC ep93xx_reg32(DMA_BASE + 0x0348)
+#define DMAMP_TX_8_STATUS ep93xx_reg32(DMA_BASE + 0x034C)
+#define DMAMP_TX_8_REMAIN ep93xx_reg32(DMA_BASE + 0x0354)
+#define DMAMP_TX_8_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x0360)
+#define DMAMP_TX_8_BASE0 ep93xx_reg32(DMA_BASE + 0x0364)
+#define DMAMP_TX_8_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0368)
+#define DMAMP_TX_8_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x0370)
+#define DMAMP_TX_8_BASE1 ep93xx_reg32(DMA_BASE + 0x0374)
+#define DMAMP_TX_8_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0378)
+
+#define DMA_ARBITRATION ep93xx_reg32(DMA_BASE + 0x0380)
+#define DMA_INTERRUPT ep93xx_reg32(DMA_BASE + 0x03C0)
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x80010000 - 0x8001FFFF: Ethernet MAC
+ */
+#define MAC_OFFSET (0x010000)
+#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET)
+
+#define MAC_RXCTL ep93xx_reg32(MAC_BASE + 0x0000)
+#define MAC_TXCTL ep93xx_reg32(MAC_BASE + 0x0004)
+#define MAC_TESTCTL ep93xx_reg32(MAC_BASE + 0x0008)
+#define MAC_MIICMD ep93xx_reg32(MAC_BASE + 0x0010)
+#define MAC_MIIDATA ep93xx_reg32(MAC_BASE + 0x0014)
+#define MAC_MIISTS ep93xx_reg32(MAC_BASE + 0x0018)
+#define MAC_SELFCTL ep93xx_reg32(MAC_BASE + 0x0020)
+#define MAC_INTEN ep93xx_reg32(MAC_BASE + 0x0024)
+#define MAC_INTSTSP ep93xx_reg32(MAC_BASE + 0x0028)
+#define MAC_INTSTSC ep93xx_reg32(MAC_BASE + 0x002C)
+#define MAC_DIAGAD ep93xx_reg32(MAC_BASE + 0x0038)
+#define MAC_DIAGDATA ep93xx_reg32(MAC_BASE + 0x003C)
+#define MAC_GT ep93xx_reg32(MAC_BASE + 0x0040)
+#define MAC_FCT ep93xx_reg32(MAC_BASE + 0x0044)
+#define MAC_FCF ep93xx_reg32(MAC_BASE + 0x0048)
+#define MAC_AFP ep93xx_reg32(MAC_BASE + 0x004C)
+#define MAC_HASHTBL ep93xx_reg32(MAC_BASE + 0x0050)
+#define MAC_INDAD ep93xx_reg32(MAC_BASE + 0x0050)
+#define MAC_INDAD_UPPER ep93xx_reg32(MAC_BASE + 0x0054)
+#define MAC_GIINTSTS ep93xx_reg32(MAC_BASE + 0x0060)
+#define MAC_GIINTMSK ep93xx_reg32(MAC_BASE + 0x0064)
+#define MAC_GIINTROSTS ep93xx_reg32(MAC_BASE + 0x0068)
+#define MAC_GIINTFRC ep93xx_reg32(MAC_BASE + 0x006C)
+#define MAC_TXCOLLCNT ep93xx_reg32(MAC_BASE + 0x0070)
+#define MAC_RXMISSCNT ep93xx_reg32(MAC_BASE + 0x0074)
+#define MAC_RXRUNTCNT ep93xx_reg32(MAC_BASE + 0x0078)
+#define MAC_BMCTL ep93xx_reg32(MAC_BASE + 0x0080)
+#define MAC_BMSTS ep93xx_reg32(MAC_BASE + 0x0084)
+#define MAC_RXBCA ep93xx_reg32(MAC_BASE + 0x0088)
+#define MAC_RXDQBADD ep93xx_reg32(MAC_BASE + 0x0090)
+#define MAC_RXDQBLEN ep93xx_reg16(MAC_BASE + 0x0094)
+#define MAC_RXDQCURLEN ep93xx_reg16(MAC_BASE + 0x0096)
+#define MAC_RXDCURADD ep93xx_reg32(MAC_BASE + 0x0098)
+#define MAC_RXDENQ ep93xx_reg32(MAC_BASE + 0x009C)
+#define MAC_RXSTSQBADD ep93xx_reg32(MAC_BASE + 0x00A0)
+#define MAC_RXSTSQBLEN ep93xx_reg16(MAC_BASE + 0x00A4)
+#define MAC_RXSTSQCURLEN ep93xx_reg16(MAC_BASE + 0x00A6)
+#define MAC_RXSTSQCURADD ep93xx_reg32(MAC_BASE + 0x00A8)
+#define MAC_RXSTSENQ ep93xx_reg32(MAC_BASE + 0x00AC)
+#define MAC_TXDQBADD ep93xx_reg32(MAC_BASE + 0x00B0)
+#define MAC_TXDQBLEN ep93xx_reg32(MAC_BASE + 0x00B4)
+#define MAC_TXDQCURLEN ep93xx_reg32(MAC_BASE + 0x00B6)
+#define MAC_TXDQCURADD ep93xx_reg32(MAC_BASE + 0x00B8)
+#define MAC_TXDENQ ep93xx_reg32(MAC_BASE + 0x00BC)
+#define MAC_TXSTSQBADD ep93xx_reg32(MAC_BASE + 0x00C0)
+#define MAC_TXSTSQBLEN ep93xx_reg32(MAC_BASE + 0x00C4)
+#define MAC_TXSTSQCURLEN ep93xx_reg32(MAC_BASE + 0x00C6)
+#define MAC_TXSTSQCURADD ep93xx_reg32(MAC_BASE + 0x00C8)
+#define MAC_RXBUFTHRSHLD ep93xx_reg32(MAC_BASE + 0x00D0)
+#define MAC_TXBUFTHRSHLD ep93xx_reg32(MAC_BASE + 0x00D4)
+#define MAC_RXSTSTHRSHLD ep93xx_reg32(MAC_BASE + 0x00D8)
+#define MAC_TXSTSTHRSHLD ep93xx_reg32(MAC_BASE + 0x00DC)
+#define MAC_RXDTHRSHLD ep93xx_reg32(MAC_BASE + 0x00E0)
+#define MAC_TXDTHRSHLD ep93xx_reg32(MAC_BASE + 0x00E4)
+#define MAC_MAXFRMLEN ep93xx_reg32(MAC_BASE + 0x00E8)
+#define MAC_RXHDRLEN ep93xx_reg32(MAC_BASE + 0x00EC)
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x80020000 - 0x8002FFFF: USB OHCI
+ */
+#define USB_OFFSET (0x020000)
+#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET)
+
+#define USB_HCREVISION ep93xx_reg32(USB_BASE + 0x0000)
+#define USB_HCCONTROL ep93xx_reg32(USB_BASE + 0x0004)
+#define USB_HCCOMMANDSTATUS ep93xx_reg32(USB_BASE + 0x0008)
+#define USB_HCINTERRUPTSTATUS ep93xx_reg32(USB_BASE + 0x000C)
+#define USB_HCINTERRUPTENABLE ep93xx_reg32(USB_BASE + 0x0010)
+#define USB_HCINTERRUPTDISABLE ep93xx_reg32(USB_BASE + 0x0014)
+#define USB_HCHCCA ep93xx_reg32(USB_BASE + 0x0018)
+#define USB_HCPERIODCURRENTED ep93xx_reg32(USB_BASE + 0x001C)
+#define USB_HCCONTROLHEADED ep93xx_reg32(USB_BASE + 0x0020)
+#define USB_HCCONTROLCURRENTED ep93xx_reg32(USB_BASE + 0x0024)
+#define USB_HCBULKHEADED ep93xx_reg32(USB_BASE + 0x0028)
+#define USB_HCBULKCURRENTED ep93xx_reg32(USB_BASE + 0x002C)
+#define USB_HCDONEHEAD ep93xx_reg32(USB_BASE + 0x0030)
+#define USB_HCFMINTERVAL ep93xx_reg32(USB_BASE + 0x0034)
+#define USB_HCFMREMAINING ep93xx_reg32(USB_BASE + 0x0038)
+#define USB_HCFMNUMBER ep93xx_reg32(USB_BASE + 0x003C)
+#define USB_HCPERIODICSTART ep93xx_reg32(USB_BASE + 0x0040)
+#define USB_HCLSTHRESHOLD ep93xx_reg32(USB_BASE + 0x0044)
+#define USB_HCRHDESCRIPTORA ep93xx_reg32(USB_BASE + 0x0048)
+#define USB_HCRHDESCRIPTORB ep93xx_reg32(USB_BASE + 0x004C)
+#define USB_HCRHSTATUS ep93xx_reg32(USB_BASE + 0x0050)
+#define USB_HCRHPORTSTATUS0 ep93xx_reg32(USB_BASE + 0x0054)
+#if (defined(EP9302) || defined(EP9307) || defined(EP9312) || defined(EP9315))
+#define USB_HCRHPORTSTATUS1 ep93xx_reg32(USB_BASE + 0x0058)
+#endif
+#define USB_HCRHPORTSTATUS2 ep93xx_reg32(USB_BASE + 0x005C)
+#define USB_CFGCTRL ep93xx_reg32(USB_BASE + 0x0080)
+#define USB_HCISTS ep93xx_reg32(USB_BASE + 0x0084)
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x80030000 - 0x8003FFFF: Raster engine
+ */
+#if (defined(EP9307) || defined(EP9312) || defined(EP9315))
+#define RASTER_OFFSET (0x030000)
+#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET)
+
+#define RASTER_VLINESTOTAL ep93xx_reg32(RASTER_BASE + 0x0000)
+#define RASTER_VSYNCSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x0004)
+#define RASTER_VACTIVESTRTSTOP ep93xx_reg32(RASTER_BASE + 0x0008)
+#define RASTER_VCLKSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x000C)
+#define RASTER_HCLKSTOTAL ep93xx_reg32(RASTER_BASE + 0x0010)
+#define RASTER_HSYNCSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x0014)
+#define RASTER_HACTIVESTRTSTOP ep93xx_reg32(RASTER_BASE + 0x0018)
+#define RASTER_HCLKSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x001C)
+#define RASTER_BRIGHTNESS ep93xx_reg32(RASTER_BASE + 0x0020)
+#define RASTER_VIDEOATTRIBS ep93xx_reg32(RASTER_BASE + 0x0024)
+#define RASTER_VIDSCRNPAGE ep93xx_reg32(RASTER_BASE + 0x0028)
+#define RASTER_VIDSCRNHPG ep93xx_reg32(RASTER_BASE + 0x002C)
+#define RASTER_SCRNLINES ep93xx_reg32(RASTER_BASE + 0x0030)
+#define RASTER_LINELENGTH ep93xx_reg32(RASTER_BASE + 0x0034)
+#define RASTER_VLINESTEP ep93xx_reg32(RASTER_BASE + 0x0038)
+#define RASTER_LINECARRY ep93xx_reg32(RASTER_BASE + 0x003C)
+#define RASTER_BLINKRATE ep93xx_reg32(RASTER_BASE + 0x0040)
+#define RASTER_BLINKMASK ep93xx_reg32(RASTER_BASE + 0x0044)
+#define RASTER_BLINKPATTRN ep93xx_reg32(RASTER_BASE + 0x0048)
+#define RASTER_PATTRNMASK ep93xx_reg32(RASTER_BASE + 0x004C)
+#define RASTER_BG_OFFSET ep93xx_reg32(RASTER_BASE + 0x0050)
+#define RASTER_PIXELMODE ep93xx_reg32(RASTER_BASE + 0x0054)
+#define RASTER_PARLLIFOUT ep93xx_reg32(RASTER_BASE + 0x0058)
+#define RASTER_PARLLIFIN ep93xx_reg32(RASTER_BASE + 0x005C)
+#define RASTER_CURSOR_ADR_START ep93xx_reg32(RASTER_BASE +
0x0060)
+#define RASTER_CURSOR_ADR_RESET ep93xx_reg32(RASTER_BASE +
0x0064)
+#define RASTER_CURSORSIZE ep93xx_reg32(RASTER_BASE + 0x0068)
+#define RASTER_CURSORCOLOR1 ep93xx_reg32(RASTER_BASE + 0x006C)
+#define RASTER_CURSORCOLOR2 ep93xx_reg32(RASTER_BASE + 0x0070)
+#define RASTER_CURSORXYLOC ep93xx_reg32(RASTER_BASE + 0x0074)
+#define RASTER_CURSOR_DHSCAN_LH_YLOC ep93xx_reg32(RASTER_BASE + 0x0078)
+#define RASTER_REALITI_SWLOCK ep93xx_reg32(RASTER_BASE + 0x007C)
+#define RASTER_GS_LUT ep93xx_reg32(RASTER_BASE + 0x0080)
+#define RASTER_REALITI_TCR ep93xx_reg32(RASTER_BASE + 0x0100)
+#define RASTER_REALITI_TISRA ep93xx_reg32(RASTER_BASE + 0x0104)
+#define RASTER_REALITI_TISRB ep93xx_reg32(RASTER_BASE + 0x0108)
+#define RASTER_CURSOR_TISR ep93xx_reg32(RASTER_BASE + 0x010C)
+#define RASTER_REALITI_TOCRA ep93xx_reg32(RASTER_BASE + 0x0110)
+#define RASTER_REALITI_TOCRB ep93xx_reg32(RASTER_BASE + 0x0114)
+#define RASTER_FIFO_TOCRA ep93xx_reg32(RASTER_BASE + 0x0118)
+#define RASTER_FIFO_TOCRB ep93xx_reg32(RASTER_BASE + 0x011C)
+#define RASTER_BLINK_TISR ep93xx_reg32(RASTER_BASE + 0x0120)
+#define RASTER_DAC_TISRA ep93xx_reg32(RASTER_BASE + 0x0124)
+#define RASTER_DAC_TISRB ep93xx_reg32(RASTER_BASE + 0x0128)
+#define RASTER_SHIFT_TISR ep93xx_reg32(RASTER_BASE + 0x012C)
+#define RASTER_DACMUX_TOCRA ep93xx_reg32(RASTER_BASE + 0x0130)
+#define RASTER_DACMUX_TOCRB ep93xx_reg32(RASTER_BASE + 0x0134)
+#define RASTER_PELMUX_TOCR ep93xx_reg32(RASTER_BASE + 0x0138)
+#define RASTER_VIDEO_TOCRA ep93xx_reg32(RASTER_BASE + 0x013C)
+#define RASTER_VIDEO_TOCRB ep93xx_reg32(RASTER_BASE + 0x0140)
+#define RASTER_YCRCB_TOCR ep93xx_reg32(RASTER_BASE + 0x0144)
+#define RASTER_CURSOR_TOCR ep93xx_reg32(RASTER_BASE + 0x0148)
+#define RASTER_VIDEO_TOCRC ep93xx_reg32(RASTER_BASE + 0x014C)
+#define RASTER_SHIFT_TOCR ep93xx_reg32(RASTER_BASE + 0x0150)
+#define RASTER_BLINK_TOCR ep93xx_reg32(RASTER_BASE + 0x0154)
+#define RASTER_REALITI_TCER ep93xx_reg32(RASTER_BASE + 0x0180)
+#define RASTER_SIGVAL ep93xx_reg32(RASTER_BASE + 0x0200)
+#define RASTER_SIGCTL ep93xx_reg32(RASTER_BASE + 0x0204)
+#define RASTER_VSIGSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x0208)
+#define RASTER_HSIGSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x020C)
+#define RASTER_SIGCLR ep93xx_reg32(RASTER_BASE + 0x0210)
+#define RASTER_ACRATE ep93xx_reg32(RASTER_BASE + 0x0214)
+#define RASTER_LUTCONT ep93xx_reg32(RASTER_BASE + 0x0218)
+#define RASTER_VBLANKSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x0228)
+#define RASTER_HBLANKSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x022C)
+#define RASTER_LUT ep93xx_reg32(RASTER_BASE + 0x0400)
+#define RASTER_CURSORBLINK1 ep93xx_reg32(RASTER_BASE + 0x021C)
+#define RASTER_CURSORBLINK2 ep93xx_reg32(RASTER_BASE + 0x0220)
+#define RASTER_CURSORBLINK ep93xx_reg32(RASTER_BASE + 0x0224)
+#define RASTER_EOLOFFSET ep93xx_reg32(RASTER_BASE + 0x0230)
+#define RASTER_FIFOLEVEL ep93xx_reg32(RASTER_BASE + 0x0234)
+#define RASTER_GS_LUT2 ep93xx_reg32(RASTER_BASE + 0x0280)
+#define RASTER_GS_LUT3 ep93xx_reg32(RASTER_BASE + 0x0300)
+#define RASTER_COLOR_LUT ep93xx_reg32(RASTER_BASE + 0x0400)
+#endif
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x80040000 - 0x8004FFFF: Graphics accelerator
+ */
+#if defined(EP9315)
+#define GFX_OFFSET (0x040000)
+#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET)
+#endif
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x80050000 - 0x8005FFFF: Reserved
+ */
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x80060000 - 0x8006FFFF: SDRAM controller
+ */
+#define SDRAM_OFFSET (0x060000)
+#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET)
+
+#define SDRAM_GLCONFIG ep93xx_reg32(SDRAM_BASE + 0x0004)
+#define SDRAM_REFRSHTIMR ep93xx_reg32(SDRAM_BASE + 0x0008)
+#define SDRAM_BOOTSTS ep93xx_reg32(SDRAM_BASE + 0x000C)
+#define SDRAM_DEVCFG0 ep93xx_reg32(SDRAM_BASE + 0x0010)
+#define SDRAM_DEVCFG1 ep93xx_reg32(SDRAM_BASE + 0x0014)
+#define SDRAM_DEVCFG2 ep93xx_reg32(SDRAM_BASE + 0x0018)
+#define SDRAM_DEVCFG3 ep93xx_reg32(SDRAM_BASE + 0x001C)
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x80070000 - 0x8007FFFF: Reserved
+ */
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
+ */
+#define SMC_OFFSET (0x080000)
+#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET)
+
+#define SMC_BCR0 ep93xx_reg32(SMC_BASE + 0x0000)
+#define SMC_BCR1 ep93xx_reg32(SMC_BASE + 0x0004)
+#define SMC_BCR2 ep93xx_reg32(SMC_BASE + 0x0008)
+#define SMC_BCR3 ep93xx_reg32(SMC_BASE + 0x000C)
+#define SMC_BCR6 ep93xx_reg32(SMC_BASE + 0x0018)
+#define SMC_BCR7 ep93xx_reg32(SMC_BASE + 0x001C)
+#if (defined(EP9307) || defined(EP9315))
+#define SMC_PCATTRIBUTE ep93xx_reg32(SMC_BASE + 0x0020)
+#define SMC_PCCOMMON ep93xx_reg32(SMC_BASE + 0x0024)
+#define SMC_PCIO ep93xx_reg32(SMC_BASE + 0x0028)
+#define SMC_PCMCIACTRL ep93xx_reg32(SMC_BASE + 0x0040)
+#endif
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x80090000 - 0x8009FFFF: Boot ROM
+ */
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x800A0000 - 0x800AFFFF: IDE interface
+ */
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x80050000 - 0x8005FFFF: Reserved
+ */
+
+
+/*
-----------------------------------------------------------------------------
+ * 0x80050000 - 0x8005FFFF: Reserved
+ */
+
+
+
diff -urP u-boot.orig-20060405/lib_arm/board.c
u-boot.scrubbed-20060405/lib_arm/board.c
--- u-boot.orig-20060405/lib_arm/board.c 2006-04-04 09:55:31.000000000
-0400
+++ u-boot.scrubbed-20060405/lib_arm/board.c 2006-04-05 09:47:49.000000000
-0400
@@ -222,6 +222,9 @@
serial_init, /* serial communications setup */
console_init_f, /* stage 1 init of console */
display_banner, /* say that we are here */
+#if defined(CONFIG_EP93XX)
+ checkcpu, /* info about CPU */
+#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo, /* display cpu info (and speed) */
#endif
diff -urP u-boot.orig-20060405/MAKEALL u-boot.scrubbed-20060405/MAKEALL
--- u-boot.orig-20060405/MAKEALL 2006-04-04 09:55:28.000000000 -0400
+++ u-boot.scrubbed-20060405/MAKEALL 2006-04-05 09:47:49.000000000 -0400
@@ -177,11 +177,13 @@
at91rm9200dk cmc_pu2 \
ap920t ap922_XA10 ap926ejs ap946es \
ap966 cp920t cp922_XA10 cp926ejs \
- cp946es cp966 lpd7a400 mp2usb \
- mx1ads mx1fs2 netstar omap1510inn \
- omap1610h2 omap1610inn omap730p2 scb9328 \
- smdk2400 smdk2410 trab VCMA9 \
- versatile versatileab versatilepb voiceblue
+ cp946es cp966 edb9301 edb9302 \
+ edb9307 edb9312 edb9315 lpd7a400 \
+ mp2usb mx1ads mx1fs2 netstar \
+ omap1510inn omap1610h2 omap1610inn omap730p2 \
+ scb9328 smdk2400 smdk2410 trab \
+ VCMA9 versatile versatileab versatilepb \
+ voiceblue
"
#########################################################################
diff -urP u-boot.orig-20060405/Makefile u-boot.scrubbed-20060405/Makefile
--- u-boot.orig-20060405/Makefile 2006-04-04 09:55:28.000000000 -0400
+++ u-boot.scrubbed-20060405/Makefile 2006-04-05 09:49:19.000000000 -0400
@@ -1464,6 +1464,36 @@
xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
+edb9301_config: unconfig
+ @echo "#define CONFIG_EP9301" >>include/config.h
+ @echo "#define CONFIG_EDB9301" >>include/config.h
+ @./mkconfig -a edb93xx arm arm920t edb93xx NULL ep93xx
+ @echo "... configured for Cirrus Logic EDB9301 board"
+
+edb9302_config: unconfig
+ @echo "#define CONFIG_EP9302" >>include/config.h
+ @echo "#define CONFIG_EDB9302" >>include/config.h
+ @./mkconfig -a edb93xx arm arm920t edb93xx NULL ep93xx
+ @echo "... configured for Cirrus Logic EDB9302 board"
+
+edb9307_config: unconfig
+ @echo "#define CONFIG_EP9307" >>include/config.h
+ @echo "#define CONFIG_EDB9307" >>include/config.h
+ @./mkconfig -a edb93xx arm arm920t edb93xx NULL ep93xx
+ @echo "... configured for Cirrus Logic EDB9307 board"
+
+edb9312_config: unconfig
+ @echo "#define CONFIG_EP9312" >>include/config.h
+ @echo "#define CONFIG_EDB9312" >>include/config.h
+ @./mkconfig -a edb93xx arm arm920t edb93xx NULL ep93xx
+ @echo "... configured for Cirrus Logic EDB9312 board"
+
+edb9315_config: unconfig
+ @echo "#define CONFIG_EP9315" >>include/config.h
+ @echo "#define CONFIG_EDB9315" >>include/config.h
+ @./mkconfig -a edb93xx arm arm920t edb93xx NULL ep93xx
+ @echo "... configured for Cirrus Logic EDB9315 board"
+
at91rm9200dk_config : unconfig
@./mkconfig $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
