Girando sui newsgroup, in particolare comp.arch.fpga (dedicato alle
logiche programmabili) ho trovato questo post sulla questione di far
passare o no un segnale di clock attraverso una porta logica, in pratica
quello che avviene nella ULA quando sospende il clock dello
Z80...
I remember reading > somewhere in this group that "gated clocks are anathema to this group". > Can someone explain what is bad about such clocks.
Short version: Putting a clock through logic leads to skew, jitter, runt pulses, and lots of other horrible things. These all make life far harder for the implementation tools, which work on the assumption that you're not a moron. FPGA logic fabric was designed for synchronous logic design. If you need to switch a clock on and off "globally" (e.g. for power saving), some devices have dedicated "clock multiplexor" resources to do this. Gate your clocks, and your designs will run slower. Your tools will run slower. Your designs will stop working inexplicably when they warm up or cool down. Your logic will cease to work when you buy a new batch of chips. Your wife will leave you for a younger man and your pot plant will die. Just don't do it! -Ben- P.S. You *really* don't want to hear the long version.credo di aver capito perche' non riesco a sincronizzare i timing del clone come l'originale.. e qui mi vengono in mente 2 cose:
