[visionegg] Re: visionegg for fMRI experiments
- From: Andrew Straw <andrew.straw@xxxxxxxxxxxxxxx>
- To: visionegg@xxxxxxxxxxxxx
- Date: Wed, 27 Nov 2002 09:55:54 +1030
On Tuesday, November 26, 2002, at 07:02 PM, Christoph Lehmann wrote:
> Thanks for your help. Concerning the parallel port: We built a
> TTL-streching circuit (flip flop) which enlarges the with of the TTL
> pulse to e.g. 50ms. Is it that what you mean with the potential
> problem:
> that TTL per se are too short to get recognized by the parallel port?
> So, do you think a low to high and back to low step, lasting for 50ms
> would be enough for your parallel port code?
Yes. I wasn't sure how long the "pulses" you originally described
were, but 50 msec should be more than enough. FYI, I just had a look
through the parallel port code to refresh my memory, and the simplest
way to read the parallel port will be something like:
from VisionEgg.DaqLPT import raw_lpt_module
input_value = raw_lpt_module.inp(0x379)
output_value = 0xFF
raw_lpt_module.out(0x378, output_value)
If you check out the development version of the Vision Egg from CVS
(instructions in the SourceForge project pages), you'll find some
slightly improved docstrings in the parallel port code, as well as a
few other bug fixes/feature enhancements, such as improved logging and
exception handling.
Cheers!
Andrew
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