[SI-LIST] Re: would vsense pin make us not worry about DC IR Drop for PI
- From: Tesla <emcesd@xxxxxxx>
- To: weirsi@xxxxxxxxxx, Istvan Novak <istvan.novak@xxxxxxxxxxx>
- Date: Fri, 21 Dec 2012 09:05:15 +0800 (CST)
Hi,
Thank you very much.
Happy holiday.
Tesla.
At 2012-12-20 22:11:54,"steve weir" <weirsi@xxxxxxxxxx> wrote:
>Istvan covered most of the high points. Orocessors can draw up to 130A
>and these requirements are managed by careful design. Your first tool
>is the copper weight in your planes. Your second tool is the location
>of the planes in the stack-up. Remote sense or other feedback
>techniques such as balanced bridge can also be used. The feedback
>method will of course affect the choice of VRM.
>
>Steve
>On 12/20/2012 12:54 AM, Tesla wrote:
>> Hi, Expert
>>
>> I found it difficult to maintain 5 percent DC voltage drop for the modern
>> FPGA, eg, Virtex6 demand 20A for the core, even if a use a complete power
>> plane.
>> The lucky thing is modern power supply chip has vsense pin to output a
>> higher voltage for compensating the DC IR drop.
>> Does that mean we need not worry DC IR drop if our power chip has the vsense
>> pin to modify the voltage?
>>
>> Thanks and happy holidays
>>
>> Tesla
>>
>>
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>
>
>--
>Steve Weir
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