[SI-LIST] Re: why "error: not increasing in time" in hspice?

  • From: "Felix Mbairi" <felix.mbairi@xxxxxxxxx>
  • To: jideguzi <jideguzi@xxxxxxx>, si-list@xxxxxxxxxxxxx
  • Date: Tue, 27 May 2008 00:46:08 -0700

Hi,


The timing in your PWL expression does not seem to increase regularly. There
might be some inconsistencies in the definitions of your parameters
"inramp_l"  and "inramp_r".

If you change the expressions to inramp_l='(mid-inramp)/2*1.25' and
inramp_r='(mid+inramp)/2*1.25', the simulation will run fine. You may also
want correct your syntaxes. I modified your netlist as shown below, and I
was able to run it without error.

*options autostop accurat runlvl

*ic v(dh)=vdd

.param vdd=3

........

.param ckramp_l='9n-ckramp/2*1.25'

.param ckramp_r='9n+ckramp/2*1.25'

.param inramp_l='(mid-inramp)/2*1.25'

.param inramp_r='(mid+inramp)/2*1.25'

.......



vsel sel 0 pwl (0p vdd 'ckramp_l' vdd 'ckramp_r' 0 13n 0)

vdh dh 0 pwl (0p vdd 'inramp_l' vdd 'inramp_r' 0 13n 0)



.tran 1p 18n UIC sweep DATA=INPUT_RAMP

.DATA INPUT_RAMP inramp ckramp  mid

                        0.015n  0.015n  13n

                        0.015n  0.015n  9n

                        0.015n  0.015n  5n

.ENDDATA



.End


Good luck,
 Felix



On 5/26/08, jideguzi <jideguzi@xxxxxxx> wrote:

> hi all
>
> I created a PWL source in my main circuit but when I run the netlist with
> hspice, it gives me error: **error** piecewise
> source        0:vdh              not increasing in time
> I have tried many ways to modified it, but failed!
> is there anybody meet the same problem like that? who can tell me where I
> am making a mistake?
>
>
> my netlist codes:
> .tran 0.001n 18n UIC sweep DATA=INPUT_RAMP
> options autostop accurat runlvl
> ic v(dh)=vdd
> ........
> param ckramp_l='9n-ckramp/2*1.25'
> param ckramp_r='9n+ckramp/2*1.25'
> param inramp_l='mid-inramp/2*1.25'
> param inramp_r='mid+inramp/2*1.25'
> .......
>
> vsel sel 0 pwl (0n vdd 'ckramp_l' vdd 'ckramp_r' 0 13n 0)
> vdh dh 0 pwl (0n vdd 'inramp_l' vdd 'inramp_r' 0 13n 0)
>
> DATA INPUT_RAMP
>        inramp  ckramp  mid
>        0.015n  0.015n  13n
>        0.015n  0.015n  9n
>        0.015n  0.015n  5n
> ENDDATA
>
>
>
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