[SI-LIST] Re: via teardropping effect on signal integrity?
- From: Guasti Giovanni <Giovanni.Guasti@xxxxxxxxxx>
- To: "'ivor@xxxxxxxxxxx'" <ivor@xxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Wed, 2 Jul 2003 17:24:46 +0200
Hi Ivor,
I think that it's difficult to recognise any difference in a PCI or LVDS
signal between the two cases: with or without teardrops. Anyway, teardrops
can help you to improve pcb reliability.
So.. I would use teardrops. And they are free too!
By
Giovanni
don't be afraid of teardrops with these low speed of signal
-----Original Message-----
From: Ivor Bowden [mailto:ivor@xxxxxxxxxxx]
Sent: Tuesday, July 01, 2003 9:56 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] via teardropping effect on signal integrity?
Hi, if I have a fairly standard stackup (sig,plane,sig,sig,plane,sig;
signal traces are 80 ohms) with .006"/.006" trace/space and .040" via
pads with .008" finished hole size, signal trace lengths of 2.5" and
7.5", would there be any significant issues with teardropping the vias?
The signals are either PCI (66MHz clock) or analog/LVDS.
tia,
Ivor Bowden
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