[SI-LIST] Re: via ?
- From: "webhugo-gcn" <webhugo@xxxxxxxxxx>
- To: <nagarwal@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sat, 28 Jun 2003 04:46:17 +0800
Hi Nimish,
How are you?
You can understand these knowledge.
Example : FEM / FDTD Numerical Method, TDR, complex via hole structures,
SPICE and IBIS.
Below is IEEE Paper.
The paper is available online as a pdf file at the IEEE Xplore website.
(http://ieeexplore.ieee.org/)
Best Regards,
Hugo Chuang
1.
Modelling complex via hole structures
Laermans, E.; De Geest, J.; De Zutter, D.; Olyslager, F.; Sercu, S.;
Morlion, D.;
Electrical Performance of Electronic Packaging, 2001 , 29-31 Oct. 2001
Page(s): 149 -152
2.
Modeling complex via hole structures
Laermans, E.; De Geest, J.; De Zutter, D.; Olyslager, F.; Sercu, S.;
Morlion, D.;
Advanced Packaging, IEEE Transactions on [see also Components, Packaging and
Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on]
, Volume: 25 Issue: 2 , May 2002
Page(s): 206 -214
3.
Analysis of via in multilayer printed circuit boards for high-speed digital
systems
Jin-Ho Kim; Sung-Woo Han; Oh-Kyong Kwon;
Electronic Materials and Packaging, 2001. EMAP 2001. Advances in , 19-22
Nov. 2001
Page(s): 382 -387
4. (*** P343 Fig16- Candance simulator SpectraQuest )
An experimental procedure to derive reliable IBIS models
Zak, T.; Ducrot, M.; Xavier, C.; Drissi, M.;
Electronics Packaging Technology Conference, 2000. (EPTC 2000). Proceedings
of 3rd , 5-7 Dec 2000
Page(s): 339 -344
5.
SPICE and IBIS modeling kits the basis for signal integrity analyses
Cuny, R.H.G.;
Electromagnetic Compatibility, 1996. Symposium Record. IEEE 1996
International Symposium on , 19-23 Aug. 1996
Page(s): 204 -208
6. Behavioral modeling for timing, noise, and signal integrity analysis
Hayes, J.D.; Wissel, L.;
Custom Integrated Circuits, 2001, IEEE Conference on. , 6-9 May 2001
Page(s): 353 -356
7.
Finite element modeling of 3D interconnection structures
Jilin Tan; Guangwen Pan;
Microwave and Millimeter Wave Technology Proceedings, 1998. ICMMT '98. 1998
International Conference on , 18-20 Aug. 1998
Page(s): 957 -960
----- Original Message -----
From: "Nimish Aggarwal" <nagarwal@xxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Friday, June 27, 2003 10:08 PM
Subject: [SI-LIST] via ?
Hi
I am new to this list. Can you tell me how to model via for signal =
integrity analysis in a multilayer boards.
What are the other requirements to do a multilayer board simulation else =
IBIS model. Need Help.
Regards
Nimish
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