[SI-LIST] Re: via ?
- From: "Dunbar, Tony" <tony_dunbar@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 27 Jun 2003 13:28:19 -0500
Nimish,
After you have explored all of the elaborate methods and sophisticated
software tools that you COULD use to model a via -- or much more preferably
BEFORE you do all that -- I respectfully suggest you re-phrase your question
to be, "How SHOULD I model a via for signal integrity?'
As is so often the answer with analysis -- it depends!
There is little to be gained (and much personal, project and CPU time to be
wasted unnecessarily) with elaborate via modeling if the rest of the
interconnect and modeling scheme is 'rough'. It's just as much a waste of
time if you're analyzing signals operating in the (say) low 100's MHz, or if
you're not including other factors such as (AC) losses, or if the
consequences of the effects (e.g. 10s of pico-seconds delay) are of little
concern or swamped by other contributors.
In short, put the via modeling issue in the context of overall problem and
proceed accordingly. Perhaps, even, describe your scenario in a re-post and
I'm sure you'll get much more concise, applicable guidance from this forum.
Regards,
Tony
-----Original Message-----
From: Nimish Aggarwal [mailto:nagarwal@xxxxxxxxxxx]
Sent: Friday, June 27, 2003 9:09 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] via ?
Hi
I am new to this list. Can you tell me how to model via for signal =
integrity analysis in a multilayer boards.
What are the other requirements to do a multilayer board simulation else =
IBIS model. Need Help.
Regards
Nimish
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