[SI-LIST] Re: unbalanced setup/hold for DDR3 read
- From: "Qu, Pingyu (Perry)" <perry.qu@xxxxxxxxxxxxxxxxxx>
- To: "hermann.ruckerbauer@xxxxxxxxxxxxx" <hermann.ruckerbauer@xxxxxxxxxxxxx>, Istvan Nagy <buenos@xxxxxxxxxxx>
- Date: Fri, 16 Apr 2010 08:51:30 -0500
Thanks, Istvan, Hermann. From what I read, read leveling is used to adjust skew
caused by fly-by topology between different byte lanes. From what you mentioned
below, it appears that the granularity of phase shift can be quite small to be
used to adjust skew within byte lane ?
For those controllers that do not have read leveling, it gets a bit tricky.
Regards
Perry
=======================================
Perry Qu
IPD Design & Qualification, Alcatel-Lucent Canada Inc.
600 March Road, Ottawa ON, K2K 2E6, Canada
Phone: 613-7846720 Fax: 613-5993642
Email: perry.qu@xxxxxxxxxxxxxxxxxx
=======================================
________________________________
From: Hermann Ruckerbauer [mailto:hermann.ruckerbauer@xxxxxxxxxxxxx]
Sent: Friday, April 16, 2010 2:30 AM
To: Istvan Nagy
Cc: Qu, Pingyu (Perry); si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: unbalanced setup/hold for DDR3 read
Hello,
this was already given for DDR2. Also here a training scheme could give the
ideal position of the Strobe what is usually different from a 90 degree phase
shift.
When setting up I timing budget I usually split up setup and hold which often
gives a negative number on one side for an ideal 90 degree shift. But when
adding up the two numbers there is still positive margin left.
and btw: this numbers are for AC/DC levels. when calculating back to Vref this
will be not that asymetric any more (if it is at all...).
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de<http://www.EyeKnowHow.de>
Hermann.Ruckerbauer@xxxxxxxxxxxxx<mailto:Hermann.Ruckerbauer@xxxxxxxxxxxxx>
Veilchenstrasse 1
94554 Moos
Tel.: +49 (0)9938 / 902 083
Mobile: +49 (0)176 / 787 787 77
Fax: +49 (0)3212 / 121 9008
schrieb Istvan Nagy:
Hello,
the answer is the read levelling feature in the DDR3 systems. check the
JESD79-3x spec at jedec.org .
This adjusts the read DLL on the DQS to balance the setup and hold margins.
regards,
Istvan Nagy
CCT
----- Original Message -----
From: "Qu, Pingyu (Perry)"
<perry.qu@xxxxxxxxxxxxxxxxxx><mailto:perry.qu@xxxxxxxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx><mailto:si-list@xxxxxxxxxxxxx>
Sent: Thursday, April 15, 2010 7:54 PM
Subject: [SI-LIST] unbalanced setup/hold for DDR3 read
Hi,
I made a small spreadsheet to help my understanding on DDR3 read timing
for DQ/DQs. Data are extracted from JEDEC spec:
DRAM speed period (ps) bit time (ps) tDQSQ(ps) tQH(ps) setup (ps) hold
(ps)
800 2500 1250 200 950 425 325
1066 1875 937.5 150 712.5 318.75 243.75
1333 1500 750 125 570 250 195
1600 1250 625 100 475 212.5 162.5
tQH = 0.38*Tck (avg) according to the spec. Setup/hold refers to the time
window between DQ and DQs when they arrive at controller after a 90 degree
phase shift (1/4 clock cycle), and calculated as:
Setup = 0.25*Tck - tDQSQ
Hold = tQH - 0.25*Tck
This is purely static timing with no SI effect taken into account. From
above, we can see there is significant unbalance between setup and hold
requirement. If we take into account clock jitter and duty cycle
distortion from controller clock output, it will be worse for the hold
side, as they directly eats into hold margin. How does one balance the
setup and hold so that we don't end up with lots of setup margin but no
margin or negative margin for hold ? Wonder where this magic 0.38 number
comes from ?
Regards
Perry
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