[SI-LIST] Re: unbalanced setup/hold for DDR3 read
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: "Qu, Pingyu \(Perry\)" <perry.qu@xxxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 16 Apr 2010 07:20:12 +0100
Hello,
the answer is the read levelling feature in the DDR3 systems. check the
JESD79-3x spec at jedec.org .
This adjusts the read DLL on the DQS to balance the setup and hold margins.
regards,
Istvan Nagy
CCT
----- Original Message -----
From: "Qu, Pingyu (Perry)" <perry.qu@xxxxxxxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Thursday, April 15, 2010 7:54 PM
Subject: [SI-LIST] unbalanced setup/hold for DDR3 read
> Hi,
>
> I made a small spreadsheet to help my understanding on DDR3 read timing
> for DQ/DQs. Data are extracted from JEDEC spec:
>
> DRAM speed period (ps) bit time (ps) tDQSQ(ps) tQH(ps) setup (ps) hold
> (ps)
> 800 2500 1250 200 950 425 325
> 1066 1875 937.5 150 712.5 318.75 243.75
> 1333 1500 750 125 570 250 195
> 1600 1250 625 100 475 212.5 162.5
>
> tQH = 0.38*Tck (avg) according to the spec. Setup/hold refers to the time
> window between DQ and DQs when they arrive at controller after a 90 degree
> phase shift (1/4 clock cycle), and calculated as:
>
> Setup = 0.25*Tck - tDQSQ
> Hold = tQH - 0.25*Tck
>
> This is purely static timing with no SI effect taken into account. From
> above, we can see there is significant unbalance between setup and hold
> requirement. If we take into account clock jitter and duty cycle
> distortion from controller clock output, it will be worse for the hold
> side, as they directly eats into hold margin. How does one balance the
> setup and hold so that we don't end up with lots of setup margin but no
> margin or negative margin for hold ? Wonder where this magic 0.38 number
> comes from ?
>
> Regards
>
> Perry
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