[SI-LIST] 回复: Re: trace impedance difference in same signal group of Intel guide

  • From: fei xue <harrison_cls@xxxxxxxxxxxx>
  • To: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 11 May 2010 10:06:06 +0800 (CST)

Hello Brian and Maoxin,
Thanks for your kind and detailed explanation, my one more doubt based on your 
comments is,

why do you think 28Ohm trace impedance for DDR control singal is better than 
37Ohm, if you look at the output buffer VI curve from IBIS model in Intel MCH 
3210 chipset, the output impedance of this buffer is 38.9Ohm shown in my first 
email below, I do think keeping 37 or 38Ohm could keep impedance continuous 
rather than 28Ohm.

Harrison



________________________________
å??件人ï¼? "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
�件人� fei xue <harrison_cls@xxxxxxxxxxxx>; "si-list@xxxxxxxxxxxxx" 
<si-list@xxxxxxxxxxxxx>
å??é??æ?¥æ??ï¼? 2010/5/9 (å?¨æ?¥) 9:18:58 ä¸?å??
主 �� [SI-LIST] Re: trace impedance difference in same signal group of 
Intel guide

Harison,

I personally have not written any guidelines that use different Zo on one 
channel vs another,
but I think I may be able to specualte what the rational for this is.  By the 
way, on a secondary 
topic, we currently recommend routing each channel on its own layer, in order 
to avoid channel
to channel out of phase coupling. However, this effect was not fully 
appreciated back in the DDR2 days,
so those guidelines often mixed signal groups from both channels within a 
layer.  One advantage of this
was to be able to do a betetr job of maintaining consistent referencing. 
Accordingly, the ballout
of the chipset was optimized with this routing in mind. So you are pretty much 
locked into it.

As far as why one channel is 28 ohms and the othe ris 37 ohms, the reason for 
this is routing space, as
my friend Maoxin mentioned previously.  Channel B tends to be worst case 
because it has to route through
the channel A connector pin field and is longer overall. So when allocating 
routing channel area we
give higher priority to channel B.  This is moot in the newer channel per 
layer guidelines, but
in the older DDR2 guidelines it does occur.  Overall CMD channel timing and 
voltage margin is better
with the 28 ohm nominal Zo, but you can not route both channels at this 
width.  So ch-B was
given priority. At least that would be my best guess.  I know this type of 
prioritization was
done in some cases.


Brian Moran
Signaling Development Group
Client Platforms
Intel Corporation

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of fei xue
Sent: Wednesday, May 05, 2010 12:12 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] trace impedance difference in same signal group of Intel 
guide

Hello all,
May I raise a question to all of you, as you know, Intel does more constraints 
restrictions than any other semiconductor vendor especially in MCH platform 
design guide (PDG). For example, in DDR2 control group signal constraints (CKE, 
CS and ODT signals) of Intel Bigby 3210 MCH chipset, the characteristic trace 
impedance of the DDR2 control group signals from MCH to Channel A dimms is 
37Ohm+/-15%, however the characteristic trace impedance from MCH to Channel B 
dimms is 28Ohm+/-10%. The traces of Channel B dimms are longer than Channel A 
dimms. My question are,

1, why is the trace characteristic trace impedance of Channel A dimms different 
from impedance of Channel B dimms.
2, I checked the IBIS model, the output buffer model of Channel A dimms is the 
same as model of Channel B dimms, they are 38.9Ohm (I got this from IBIS VI 
curves), so it is not the reason of buffer output impedance.
3, I do not think the trace impedance's difference is because of trace distance 
difference between Channnel A and Channel B, 37Ohm and 28Ohm are big gaps.
4, PCB manufactory gave us feedback that they can not control trace impedance 
within 28Ohm+/-10%, what they can do is controlling impedance within 
28Ohm+/-5Ohm, how to evaluate this impact? can we confirm with manufactory that 
controlling impedance within 28Ohm+/-5Ohm is ok or not.

I appreciate if you have any hints on this.

Harrison


      
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