[SI-LIST] Re: the difference of current profile between power supply path, signal path and return path in a circuit loop

  • From: xuzhengrong <xuzhengrong@xxxxxxxxxx>
  • To: helen.tao.xu@xxxxxxxxx
  • Date: Tue, 04 Sep 2007 10:42:49 +0800

Helen,
I have realized that I confuse current in the main path and that in the
branch. =20
Kirchhoff's current law is right for all circuit .
It is important to recognize whether it is the main path or not. =20
Thanks for your advice.

Best Regards,
Zhengrong




-----=D3=CA=BC=FE=D4=AD=BC=FE-----
=B7=A2=BC=FE=C8=CB: si-list-bounce@xxxxxxxxxxxxx =
[mailto:si-list-bounce@xxxxxxxxxxxxx]
=B4=FA=B1=ED tao xu
=B7=A2=CB=CD=CA=B1=BC=E4: 2007=C4=EA9=D4=C24=C8=D5 8:58
=CA=D5=BC=FE=C8=CB: xuzhengrong@xxxxxxxxxx
=B3=AD=CB=CD: Benny Yan; si-list@xxxxxxxxxxxxx
=D6=F7=CC=E2: [SI-LIST] Re: the difference of current profile between =
power supply
path, signal path and return path in a circuit loop

Hi, Zhengrong,
I think the key for this question is if this component can be treated as =
a
node in your analysis. If the answer is yes, the description above is
correct. but if it is not, we should think more.

for one buffer case, I guess it is easy to simplify it as a node since =
power
pin, group pin and signal out pin is assumed at same location. and a =
quick
solution can be drawn that output current in signal path is same as one =
in
return path. (input current is too small to be ignored)

But for a whole chip, we always can not treat it at node in current =
signal
speed and must considered its distribution characters. no such ONE node =
as
above can be created.

Thanks and Regards
Tao ( Helen )

On 8/31/07, xuzhengrong <xuzhengrong@xxxxxxxxxx> wrote:
>
> Benny,
> I know my question is so basic and seems to be ridiculous.
> What I interest is how to get the current profile for voltage noise=20
> simulation associated with PDN, for it is hard to get the current =3D=20
> profile of ICs in the power rail from IC supplier.
> Though there's a method to get current profile by voltage tests =3D=20
> indirectly, I'm still interested in getting it by direct tests.
> So I ponder upon the problem whether it exits a path I can test simply =

> =3D and accurately?
>
> Zhengrong
>
>
>
>
>
> -----=3DD3=3DCA=3DBC=3DFE=3DD4=3DAD=3DBC=3DFE-----
> =3DB7=3DA2=3DBC=3DFE=3DC8=3DCB: Benny Yan [mailto: =
zyan@xxxxxxxxxx]=3D20
> =3DB7=3DA2=3DCB=3DCD=3DCA=3DB1=3DBC=3DE4: =
2007=3DC4=3DEA8=3DD4=3DC230=3DC8=3DD5 21:20
> =3DCA=3DD5=3DBC=3DFE=3DC8=3DCB: xuzhengrong@xxxxxxxxxx; =
si-list@xxxxxxxxxxxxx
> =3DD6=3DF7=3DCC=3DE2: RE: [SI-LIST] the difference of current profile =
between=20
> =3D power supply path, signal path and return path in a circuit loop
>
> Forgot Kirchhoff's current law?
> =3D20
>
> Benny Yan
> IO Methodology Inc.=3D20
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=20
> [mailto:si-list-bounce@xxxxxxxxxxxxx ] =3D On Behalf Of xuzhengrong
> Sent: Thursday, August 30, 2007 8:34 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] the difference of current profile between power =3D =

> supply path, signal path and return path in a circuit loop
>
> Hi all,
> After scanning the discussion about the return path,  I  have to think =

> =3D such a question that, what does the  current profile in power=20
> supply, signal =3D path and return path in a circuit loop look like, =
and=20
> what is the difference =3D of the three ones?
> As is known to all,  in a simple DC circuit such as small bulb loop, =
=3D=20
> current supply is equal to the return current between possive pole and =

> negative pole.
> Then, in a high speed digital circuit,  if only one buffer works and =
=3D=20
> outputs one signal level(excluding multi-signal use the common return=20
> path and =3D power supply path ), would current profiles in the signal =

> path and its return =3D path be the same?
> Furthermore,  as the source of the signal current,  what is the =3D=20
> difference between  the current profile in the power supply path and=20
> its signal =3D current profile?
>
> Thanks for any idea.
>
> Zhengrong
>
>
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