[SI-LIST] Re: termination on cpci
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: pietrov@xxxxxxxxxxxxxxx
- Date: Fri, 28 Mar 2014 08:40:08 -0400
Pietro,
Back in the 90's when I was designing PCI-based servers at Intel, we were
designing long PCI busses with a large number of peripheral slots and
on-board components. Undamped overshoot rattling around the bus caused
huge timing pushouts. The solution was to use series damping resistors.
The optimal solution for those busses was to divide the bus into thirds
and place resistors at the 1/3 and 2/3 points. Those resistors were tuned
through simulation for optimal operation across device corners, and would
end up being between 10 and 22 ohms, depending on the length of the bus.
For short busses, a single resistor at the approximate center would work
just fine. It would tend to be 22 to 33 ohm for best operation.
CPCI took a higher cost approach that placed the resistors on the cards,
where they are not as effective, but relieved designers of having to
engineer the system board bus.
You are on the right track.
regards,
Scott
On Fri, Mar 28, 2014 at 6:51 AM, pietro <pietrov@xxxxxxxxxxxxxxx> wrote:
> Hello expert.
>
> Reading document PICMG 2.0 R3.0 (Oct 1999), I see Compact PCI "standard"
> assumes many bussed PCI signals to include 10Ohm series stub termination.
> In the same document there is a long list of signals
> (AD-031,CBExx,.......) that should comply with that and those R should
> be close to the PCI connector.
>
> My understanding is that is true if your design is done by a System
> board (primary card), the backplane and the PCI peripheral.
>
> Question:
>
> what about if the PCI bus is on the same board (no backplane in between
> driver and receiver ) ?
>
> Running a simulation I found that a R series set in between the two
> components might be necessary as will clean the signals reducing over
> and undershoot: do you think is the right approach ?
>
> Thanks
>
> Pietro
>
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--
Scott McMorrow
Teraspeed Consulting Group LLC
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http://www.teraspeed.com
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