[SI-LIST] Re: termination for routing 8 SDRAMs to single Proc essor
- From: "Grasso, Charles" <Charles.Grasso@xxxxxxxxxxxx>
- To: 'Douglas Burns ' <dburns@xxxxxxxxxx>, ''for_si_list ' ' <for_si_list@xxxxxxxxx>, "'si-list-bounce@xxxxxxxxxxxxx '" <si-list-bounce@xxxxxxxxxxxxx>, "'si-list@xxxxxxxxxxxxx '" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 12 Aug 2005 12:48:01 -0600
OK - That makes sense. Thanks!!
-----Original Message-----
From: Douglas Burns
To: Grasso, Charles; 'for_si_list '; si-list-bounce@xxxxxxxxxxxxx;
si-list@xxxxxxxxxxxxx
Sent: 8/12/2005 11:33 AM
Subject: RE: [SI-LIST] Re: termination for routing 8 SDRAMs to single
Processor
Charles,
I think you misunderstood the values next to the Tlines in the document.
We
were discussing topology lengths on the SoDimm, so the values next to
the
Tline segments are in "mils" not impedance. This should have better
documented
in the figure. In terms of impedance, a nominal 60ohm environment is
assumed.
Best regards,
Doug
Douglas Burns
Vice President, Consulting Services/Chief Consultant
Signal Integrity Software, Inc.
6 Clock Tower Place
Maynard, MA 01754
978-461-0449 x14
dburns@xxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Grasso, Charles
Sent: Friday, August 12, 2005 12:34 PM
To: 'for_si_list '; 'si-list-bounce@xxxxxxxxxxxxx ';
'si-list@xxxxxxxxxxxxx '
Subject: [SI-LIST] Re: termination for routing 8 SDRAMs to single
Processor
Hello,
I looked at the balanced topology described in the SiSoft DesignCon
paper. I
have a question on the manufacturabilty of the *VERY* high Zo
topologies.
Whilst very easy to implement in a simulator - the limitations on trace
widths and plane separation would indicate that very high Zo boards are
impractical.
Are high volume manufacturers actually using the high Zo topologies?
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
To: si-list@xxxxxxxxxxxxx
Sent: 8/11/2005 6:32 AM
Subject: [SI-LIST] Re: termination for routing 8 SDRAMs to single
Processor
Hi Alex,
For Address Bus, Refer any of the JEDEC Reference Design
Specification's/Raw Cards for DDR DIMM's/SODIMM's and you will find a
number of Topologies for the Address Bus without a Termination. Make
sure u do all the length matching as mentioned though.
You should even consider routing the Address/Command bus as in DDR2
DIMM modules, where the routing is Balanced unlike DDR1 modules.
Refer Page 18 of below link:
http://www.sisoft.com/pdf/DDRII_DesignCon_2005_paper.pdf
Even in the Case of Registered Memory modules, Post-Registered
Address Bus have no single termination on it. Moreover, the JEDEC
spec allows for 4.5 V/ns overshoot on the Address bus, which would
easily be met even without any termination.
The best way to route the Data bus would be a "Balanced T Topology".
However, With a 4 load Topology, there would be severe reflections
from the Stubs of other 3 devices especially during the READ's, if
stubs are long.
Make sure the branches after the T point are kept short.
If X is the stub length, then
2X [Round Trip time] should be < 1/3 rd Rise time of the Driver [DDR
SDRAM], so that the reflection's are masked by the inertia of the
Driver's Rising Edge.
Whether Termination's are required or *NOT* depends on many factors
like:
[1] Driver Output Impedance
[2] Receiver Input Impedance
[3] Transmission Line Impedance
[4] Combination of Line Length & Driver Rise time
Its very important to make Reflection coefficient ZERO either
at the Driver end or at the Receiver end to prevent any reflection.
I feel its better you have Pull Up's for Data at the Memory
Controller to facilitate "READS".
Best Regards,
Member-SI List
--- In si-list@xxxxxxxxxxxxxxx, Aravnda G <aavinda12@xxxx> wrote:
> Hi All,
> I am working with a micro-processor conneted to 8 SDRAM with 12
address lines to all SDRAMs and 32 data lines each to two sets of
four SDRAMs. I was wondering if anyone has managed to route this sort
of topology without using terminations. If so please send information
on topology used. The IO are lvttl compatible at 3.3V. Any input on
routing possibilities is welcome.
>
> Thanks & Regards,
> Alex.
>
> ---------------------------------
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