[SI-LIST] Re: spice modeling for organic build-up substrates
- From: Pat Diao <Pat_Diao@xxxxxxxx>
- To: 'Javier DeLaCruz' <jdelacruz@xxxxxxxxxxxx>
- Date: Fri, 17 Jan 2003 16:11:05 -0800
Javier,
Thanks for the info.
Following this thread to a slightly different direction. Etching process
always creates an slope on the side of the trace. This slope is about 19
degree from the 90 degree vertical wall, from studying the substrate layers.
The designed trace width is controlled to be the bottom trace width.
Compare this trapezoidal cross-section to the rectangular cross section
which is usually generated in most 3D modeling software, my study shows a
difference of anywhere between 10-20% in differencial impedance, depending
on the width/spacing ratio.
Some 2D simulators have the ability to generate trapezoidal cross sections.
3D simulators generally can only vertically extrude traces from 2D design
file.
Personally I adjust trace width on simple geometries to compensate the
effect. Will appreciate any comments and sharing on how to better deal with
the problem.
Pat
Pat Diao, Ph.D.
Manager - Package Thermal, Electrical
and Mechanical Engineering and Development
ASAT Inc.
Fremont, CA
phone: (510) 249-1227
cell: (408) 666-2285
pat_diao@xxxxxxxx
-----Original Message-----
From: Javier DeLaCruz [mailto:jdelacruz@xxxxxxxxxxxx]
Sent: Friday, January 17, 2003 2:56 PM
To: Pat Diao
Cc: Si-List (E-mail); apannikk@xxxxxxxxxx
Subject: RE: [SI-LIST] Re: spice modeling for organic build-up
substrates
Pat,
You guessed right. The roughening is an adhesion improvement. It
looks like all of the major organic build-up suppliers have similar
processes since the cross sections look similar. The roughening seems
to be about 2-3um in in depth (peak to valley) and it tends to round off
the corners of the traces as well.
In conventional organic substrates where the BT copper layers are
metal foil (1/4 oz and above,) the roughening is not a significant
percentage of the trace height and width. Alternatively, in build-up
layers, which are sputtered and then plated, a 2um variation on all sides
is significant.
I received a bunch of direct responses to this note and I appreciate
all of the input. It appears this is a very common problem and that most
people just use two design files, one for fabrication, and one for
simulation. Some people tend to use "move face" commands on the
simulation tools after the designs were imported as well, which seems to
be a substantial amount of work when simulating multiple nets.
Thanks,
Javier
-----Original Message-----
From: Pat Diao [mailto:Pat_Diao@xxxxxxxx]
Sent: Friday, January 17, 2003 5:05 PM
To: 'apannikk@xxxxxxxxxx'; Javier DeLaCruz; Si-List (E-mail)
Subject: RE: [SI-LIST] Re: spice modeling for organic build-up
substrates
Could anyone give a clear description about the substrate trace "roughening"
process?
My impression is that the process "roughens" the Cu layer surface to make it
sticking to BT beeter. Therefore it should not cause significant change to
trace thickness and width.
Thanks,
Pat
-----Original Message-----
From: Anil Pannikkat [mailto:apannikk@xxxxxxxxxx]
Sent: Thursday, January 16, 2003 12:18 PM
To: 'jdelacruz@xxxxxxxxxxxx'; Si-List (E-mail)
Subject: [SI-LIST] Re: spice modeling for organic build-up substrates
Javier
We have struggled with this issue too and so far dealt with it by
using two different designs (one for fab and one for simulation). The
problem is that different substrate vendors could have different offsets. I
have simulated impedances using manufactured x-section values and still come
up with the offset you are talking about.
Thus so far we have relied on initial test measurements to tell us
what the offset is, gone back to the drawing board in SI2D to match the
measurements and redrew future designs to incorporate the changes for
simulation purposes.
It is pretty easy in package design programs like APD to change the
widths of nets and then transfer the info to HFSS/SI3D etc.
Regards
Anil
Anil Pannikkat
MTS Package Development * : 408-544-7542
Altera Corporation Fax: 408-544-6404
101, Innovation Drive, M/S 4202 *: apannikk@xxxxxxxxxx
San Jose, CA 95134 *: http://www.altera.com
-----Original Message-----
From: Javier DeLaCruz [mailto:jdelacruz@xxxxxxxxxxxx]
Sent: Thursday, January 16, 2003 12:01 PM
To: Si-List (E-mail)
Subject: [SI-LIST] spice modeling for organic build-up substrates
All,
I'm looking for some help in modeling organic build-up package =
substrates in order to output spice models, etc. The trick here is that =
in order attain a 100 ohm differential pair, the common mode impedance =
must be designed to a 85-88 ohm target. During manufacture, the traces =
are roughened which reduces the height, and more importantly, the width = of
the traces. This reduction in capacitance to ground, and the = increase in
both resistance and inductance causes the lines to increase = in impedance
about 15%. This means using the extraction routines in = software such as
Cadence APD/APE or Ansoft SIwave/Q3D would generate = incorrect spice models
since they were designed (in CAD) to have an = 85-88 ohm impedance. =20
Does anyone have an idea of how to generate a negative offset in
height = and width of traces in any of these programs, or any other popular
= package design/analysis package? I'd like to avoid having to generate =
two designs for each package substrate. One would be for the = fabrication
masks, and the other would represent reality.
Thanks,
Javier DeLaCruz
Sr. Principal Packaging Engineer
eSilicon Corporation
890 Mountain Avenue
Murray Hill, NJ 07974
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