[SI-LIST] Re: small device de-embedding & modeling
- From: Heyfitch <heyfitch@xxxxxxxx>
- To: Brecht Machiels <brecht.machiels@xxxxxxxxxxxxxxxx>
- Date: Tue, 13 Apr 2010 10:54:57 -0500
Hello Brecht,
first, this is probably the wrong group for the topic you brought up. Yet,
I'll try to share my limited experience with this (up to 18GHz).
A transistor RF model is usually made of 1) the core base band model, and 2)
RF "envelope" of parasitics around the active device, which is meant to
model the BEOL interconnect. The baseband model is fitted first with
BSIMPro+ or ICCAP. When you get a foundry PDK, the RF part of the model is
often interpolated between the pre-solved geometries. Those geometries are
better to have been characterized. But instead, they are usually
field-solved using a "calibrated field solver." Here the word "calibrated"
means that a few geometries were once characterized and the field solver
parameters - such as the dielectric constant for example - have been fudged
to give a matching solution.
It's no surprise that at high frequencies you have difficulties even if you
perform the de-embedding correctly. Before you begin to de-embed, you make
an assumption about the equivalent circuit that represents the BEOL jig
around your DUT, which connects the probe tips to the DUT. The fieldsolver
(Momentum in this case), you use for emulation, "makes its own assumptions"
by not taking into account some modes. There was a paper from IBM and Sonnet
about resolving discrepancy between the measurements of a spiral inductor
and the field-solver predictions. (Search Sonnet's website for the paper.)
They found that the gap between the measurements and simulations is closed
once the leakage resistance thru the p- substrate to the chuck is taken into
account. Also, field solvers vary greatly in how well they perform numerical
de-embedding. It is another significant source of error. I am not the most
qualified person here on this list to explain this. Hopefully, the right
people will see this thread and chime in on the subject.
Also, at 100GHz I would think that a simple open-short de-embedding is not
sufficient. You may have to assume several Z and Y sections alternating
between the probe tip and the DUT. Hence, the de-embedding would involve
several peeling layers. With sufficient number of elements / parameters you
should be able to fit anything. At that point the accuracy of your
measurements and how well you de-embedded to the probe tips become the
source of error. NIST website should have good papers on this topic. Also,
SUSS (in Dresden) has much experience in this and is worth talking to.
-Vadim
On Tue, Apr 13, 2010 at 3:50 AM, Brecht Machiels <
brecht.machiels@xxxxxxxxxxxxxxxx> wrote:
> Hi,
>
> I would like to obtain measurements of MOSFETs that are valid up to high
> frequencies (110GHz). Unfortunately, I'm not familiar with de-embedding.
> I'm currently investigating a number of de-embedding techniques:
>
> http://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumber=830987&queryText%3D.QT.A+four-step+method+for+de-embedding+gigahertz.QT.%26openedRefinements%3D*%26searchField%3DSearch+All
>
> http://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumber=4141067&queryText%3D.QT.Efficient+De-Embedding+Technique+for+110-GHz+Deep-Channel-MOSFET+.QT.%26openedRefinements%3D*%26searchField%3DSearch+All
>
> I've given the first of these a quick try by emulating a measurement
> using a test fixture (unlikely to be optimal) and dummy structures
> simulated in ADS momentum. Afterwards, I insert a MOSFET model into the
> test fixture using HSPICE. From the obtained S-parameters I can perform
> de-embedding.
>
> For large MOSFETs (W > 32 um), the de-embedded S21 and S12 are indeed
> very close to the model's S21 and S12. S11 and S22 are less closely
> matched to the model's, but still close. At higher frequencies (> 80
> GHz), the error becomes larger.
>
> For small MOSFETs, the de-embedded measurements only fit the model at
> lower frequencies. I assume this is to be expected as the DUT's
> properties become smaller compared to the test fixtures.
>
> Also, the articles on de-embedding I have read/scrolled through always
> use large MOSFETs for the DUT (W > 64 um) when verifying the presented
> de-embedding technique.
>
> This makes me wonder how typical transistor models are developed. I
> assume a number of large transistors are measured to which a model is
> fitted (BSIM, for example). Smaller transistors are modeled by means of
> an implicit extrapolation. Could that be anywhere near how it's done?
>
> Unfortunately, I need to use small transistors (W as small as 2 um) in
> my design, so I'm not sure how to continue from here. Any suggestions?
>
> Kind regards,
> Brecht
>
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