[SI-LIST] Re: simulate ibis model in hspice ???

  • From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxx>
  • To: "si-list" <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 3 Dec 2002 10:37:32 -0500

IBIS models that don't have Waveform data, have no timing reference for
looking at delays.  You can draw no conclusions from them about rising
versus falling delay differences.

They are useful for simulating rising edges, and for simulating falling
edges, but not for comparing the two.

Even if they had Waveform data, there is no reason for the delay
"through" an IBIS model to have any relationship to reality, nor to the
delay through a SPICE model of the same device.

IBIS models represent the characteristics of the output pin as if it
were a 1-port device, whereas most SPICE models represent some portion
of circuitry within the IC.  The delay through the SPICE model would
depend on how much of the IC's circuitry was included in the SPICE
model.  There is no similar concept with IBIS models.

Regards,
Andy


---
>   When compared the result of each other they are
>   similar in general. But the timing delay is different ,for rising
>   edge , the spice model's  result have more delay than IBIS's , it's
>   about 1.58ns. but for falling edge ,the IBIS model have more delay
>   about 330ps .  so the result looks like spice result pulse width
>   was a little narrow than the IBIS result.
> 
>   The ibis model doesnt have Rising and Falling Wave , which only have
>   the Ramp, but without R_load . looks like it
> 
>   .....
>   .......
> [Ramp]
> |  variable       typ          min          max
> |
> dV/dt_r        1.88/0.57n   1.67/0.89n   2.08/0.38n
> dV/dt_f        1.91/0.50n   1.72/0.78n   2.09/0.34n
> 
> [End]  
> 
>  Has anyone done work in this and know how to solve it ?
>  any help is appreciated :-)
> 
> 

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