[SI-LIST] Re: si-list Digest V4 #261
- From: Ivan Ndip <ndip@xxxxxxxxxxxxxxxxx>
- To: gstokes@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Tue, 06 Jul 2004 12:23:00 +0200
Hi Geoff,
the feeding lines are considered as ideal, so as to capture only the
effects of the via. The goal is to obtain the inductance of a through
via (of course, with its pads) using HFSS, not a complete
characterization of all traces and discontinuities in the package or
PCB using one HFSS model. If all these are to be considered in one HFSS
model, then the computation time and memory will be so large, that the
simulation might not even come to an end.
The traces can be characterized separately, and if they are uniform over
a given length, then 2D field solvers can also be used.
Certainly, the inductance of a signal via depends on the location of the
current path associated with the via. If the vias are closely repeated
in a region as you say, then the inductance becomes a function of the
positions of all the nearby vias. This must be considered as well.
Regards,
Ivan Ndip
Geoff Stokes wrote:
>I think this is helpful but might not be a complete discussion. It seems to
>assume that the wave modes on the connecting copper microstrips or
>striplines are well-characterised. The de-embedding normally uses the
>simplest wave mode. This will often not be representative, particularly in
>a dense board layout situation. I'm not exactly sure how to address it, but
>I have noticed that the current flow around the via is quite complicated.
>The impedance is quite sensitive to via position. Ideally, rather than a
>single via, the vias should be closely repeated in a region. In some RF
>applications, to get much lower effective inductance on a ground connection,
>instead of a row of vias, the board is milled with a slot before plating.
>Again, the positioning of the slot will be critical.
>
>
>
>>-----Original Message-----
>>From: Ivan Ndip [mailto:ndip@xxxxxxxxxxxxxxxxx]
>>Sent: 01 July 2004 10:18
>>To: kpalusa@xxxxxxxxx; si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Re: si-list Digest V4 #261
>>=20
>>=20
>>Hi,
>>you have to first develop an EM model of the via, together with the=20
>>planes in HFSS. Use feeding lines to connect the via to the=20
>>wave ports.=20
>>Assign materials to the model, define the ports and set up the=20
>>convergence criteria (e.g., maximum delta_S). At the end of the field=20
>>simulation, remove the effects of the feeding lines through=20
>>de-embedding. You can now use the resulting S-parameters to=20
>>extract the=20
>>electrical parameters (e.g., inductance, capacitance,...) of the via.=20
>>One way of doing this is to use a circuit simulator (e.g.,=20
>>Serenade from=20
>>Ansoft, ADS,...). Based on the extracted S-parameters, develop and=20
>>equivalent circuit model of the via and through optimization, these=20
>>electrical parameters can then be obtained.
>>=20
>>Best regards,
>>Ivan Ndip
>>=20
>>=20
>>kusuma palusa wrote:
>>=20
>>
>>
>>>Hello,
>>>=20
>>>Can somebody please suggest how to extract inductance of a=20
>>>
>>>
>>through via from HFSS
>>
>>
>>>=20
>>>Thanks
>>>
>>> =09
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>>=20
>>=20
>>--=20
>>**************************************************************
>>*************
>>Dipl.-Ing. Ivan N. Ndip
>>Research Engineer
>>=20
>>Fraunhofer Institut f=FCr Zuverl=E4ssigkeit und Mikrointegration (FhG-IZM)
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