Anto - thanks for the equation. I will have to look into this one!
Steve - PDN impedance flatness is not a requirement. The PDN response to a
step current is Z0*I_step. This works particularly well when Z0 is the
characteristic impedance of a "Bandini Mountain" resonant peak that rises off a
flat impedance profile. The equation is used to calculate the droop from a
step current, or alternatively to find the maximum step current that can be
sustained by a given impedance peak with acceptable voltage droop.
The V=I_Step*Zo*Q*4/PI equation gives the peak-to-peak voltage of a resonance
waveform that builds up over time with from a load with current pulses that are
I_Step high and repeating at the PDN resonant frequency. The voltage droop
from this waveform is half of this p-p waveform, added onto the "DC voltage
drop" associated with the waveform. The p-p waveform often goes both above and
below the nominal PDN voltage because of resonance phenomenon.
For much more detail on these equations, please see Chapter 9 of "Principles of
Power Integrity for PDN Design."
regards,
Larry Smith
________________________________
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> on behalf of
Anto Kavungal Davis <antokdavis@xxxxxxxxx>
Sent: Monday, July 31, 2017 10:11:45 AM
To: ssandler1@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: si-list Digest V17 #165
Hi all,
If anybody is interested in a general equation for antiresonant peak value
for two capacitors in parallel with their mounting loops coupled with a
coupling coefficient k is,
Zp <= (Rc^2 + R1R2)/(R1 + R2) where Rc = sqrt(L1L2(1-k)/(C2(L1+L2)).
R1 and R2 are ESR of the two capacitors and varies with frequency and
temperature.
Applying approximations will give Zp <= (L1/(C2 ESR)) for this case.
The equation can be used for a plane-capacitor pair with approximations.
Interested people can read,
http://ieeexplore.ieee.org/document/7600488/
If anybody is interested in suppressing the antiresonant in a *"different"*
way/method can look into this method,
http://ieeexplore.ieee.org/document/7492379/
Regards,
Anto
On Mon, Jul 31, 2017 at 11:31 AM Steve Sandler <ssandler1@xxxxxxx> wrote:
Let's see if the 3rd time is the charm. I don't know why sometimes my
messages are garbled and sometimes they are not. They are all sent using
Outlook.
The voltage excursion, V is equal to the product of Zo, which is the
SQRT(L/C) and I_step, but only for flat impedance structures. Otherwise,
the voltage step is equal to
V=I_Step*Zo*Q*4/PI where Q is approximately Zo/ESR.
The 4/PI term is the fundamental Fourier component of a square wave
excitation and Zo/Q is the peak impedance.
This relationship also shows why controlled (high) ESR ceramic capacitors
can be so effective in REDUCING the transient, which seems
counterintuitive.
Steve
-----Original Message-----
From: FreeLists Mailing List Manager [mailto:ecartis@xxxxxxxxxxxxx]
Sent: Saturday, July 29, 2017 10:09 PM
To: si-list digest users <ecartis@xxxxxxxxxxxxx>
Subject: si-list Digest V17 #165
si-list Digest Sat, 29 Jul 2017 Volume: 17 Issue: 165
In This Issue:
#1: From: Abe Riazi <riaziabe@xxxxxxxxx>
Subject: [SI-LIST] Re: Plane impedence and Target impedence
#2: From: "xiaoguang.wang" <xiaoguang.wang@xxxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Seasim - port definition for s4p
files
----------------------------------------------------------------------
Msg: #1 in digest
From: Abe Riazi <riaziabe@xxxxxxxxx>
Date: Sat, 29 Jul 2017 10:57:57 -0700
Subject: [SI-LIST] Re: Plane impedence and Target impedence
Hi Sanjeev,
I agree that such system level simulations offer a more accurate approach
for determining PDN noise and resonant peaks, as compared to use of
mathematical formulae.
Of course, the equations stated by Larry furnish useful insight and a quick
method for computing the Bandini Mountain frequency and impedance values,
provided that the on-die capacitance (C) and the bump loop inductance (L)
are accurately known.
Thanks and with kind regards,
Abe
On Fri, Jul 28, 2017 at 9:02 PM, Sanjeev Gupta <
sanjeev@xxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
transient PDN noise simulation either using IBIS model(SSN aware) orissues, if any..
using SPICE IO models along with extracted PDN models
(die+package+PCB) running using PRBS15 pattern for a very long
duration simulation time can surely capture potential 75MHz PDN noise
Don't be afraid of running long hours simulations using SPICE setup.dependent.
SPICE setup can further be optimized using current mirror methods to
reduce simulation time.. :)
Thanks
Sanjeev
On Sat, Jul 29, 2017 at 8:47 AM, Larry Smith <larry.smith@
pdnpowerintegrity.com> wrote:
Abe - yes, there is a simple formula for the Bandini Mountain Frequency.
The major PDN impedance peak is at f0 = 1/(2*pi*sqrt(LC)). C is the
on-die capacitance and L is the bump loop inductance. The bump loop
inductance is the inductance seen looking out through the package
bumps to the mounted board capacitors.
There is an equally useful formula for the characteristic impedance of
Bandini Mountain. It is Z0 = sqrt(L/C). The PDN voltage droop from a
fast step current is found from Z0. V_step_droop = Z0 * I_step.
This is the PDN step response.
These are two of the most important formulas that characterize the
major PDN resonant peak.
regards,
Larry Smith
________________________________
From: Abe Riazi <riaziabe@xxxxxxxxx>
Sent: Friday, July 28, 2017 6:58:27 PM
To: Larry Smith
Cc: si-list; ArunKumar.K@xxxxxxxxxxxxxxxxxxx; arunka97@xxxxxxxxx
Subject: Re: [SI-LIST] Re: Plane impedence and Target impedence
Hi Larry,
Is there a mathematical formula for computing the "Bandini Mountain
Frequency", mentioned in your email?
Thank you in advance for your response.
Abe
On Fri, Jul 28, 2017 at 10:52 AM, Larry Smith <
larry.smith@xxxxxxxxxxxxxxxxxxxxx<mailto:larry.smith@
pdnpowerintegrity.com>> wrote:
Arun - the on-die capacitance determines the PDN impedance above a
certain frequency. This frequency is almost certainly below 800 MHz.
It is the frequency where the inductive board impedance crosses the
on-die capacitance impedance.
Most products have a frequency band where the PDN impedance exceeds
target impedance even after the on-die capacitance is considered. It
seems that for you, this starts at 75 MHz. Exceeding the target
impedance represents PDN risk but it is often too expensive to fix
it. Some of us call this PDN impedance peak "Bandini Mountain."
The important questions then become: How much transient current do we
have at Bandini Mountain frequency? How much PDN noise will the
circuits tolerate in this frequency band? These are often difficult
questions with no easy answers. For DDR, it will be signal pattern
regards,
Larry Smith
________________________________
From:
si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx> <
si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx>> on
behalf of Arun Kumar K <ArunKumar.K@xxxxxxxxxxxxxxxxxxx>
Sent: Tuesday, July 25, 2017 10:30:51 PM
To: si-list
Cc: arunka97@xxxxxxxxx<mailto:arunka97@xxxxxxxxx>
Subject: [SI-LIST] Plane impedence and Target impedence
Hi Experts,
I am small doubt in Power integrity.
I did the power integrity one of the baord which is having DDR3 which
will work at 800MTps.
But all power, related to DDR are crossing the target impedence
around 75MHz.
Is this necessary to keep the plane impedence under the target
impedence up to 800MHz?
If yes ->, if not -> why?
Thanks & Regards
Arunkumar K
L&T Technology Services Ltd
www.LntTechservices.com<http://www.LntTechservices.com><http<http://www.LntTechservices.com<http://www.LntTechservices.com><http>
://www.lnttechservices.com/<http://www.LntTechservices.com<h
ttp://www.lnttechservices.com/>>
This Email may contain confidential or privileged information for the
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do not use or disseminate the information, notify the sender and
delete it from your system.
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------------------------------
Msg: #2 in digest
Date: Sun, 30 Jul 2017 12:39:51 +0800
Subject: [SI-LIST] Re: Seasim - port definition for s4p files
From: "xiaoguang.wang" <xiaoguang.wang@xxxxxxxxxxxxxx>
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