Luckily capacitor models today tend to be more decent today, and I would
say any vendor data based on measured S11 would be the exception, not
the norm. We do need to be careful though, because even properly
generated capacitor models tend to be two-port models, in which case we
may need to use S21 in our simulations and ignore S11.
Regards,
Istvan Novak
Oracle
On 1/13/2016 12:37 PM, Steve@xxxxxxxxxxxx wrote:
A few things to recognize, folks
First, ANYONE can build an averaged model which is state space plane
supporting AC analysis (impedance, PSRR, etc.). Second it is not generally
possible to assume small signal performance, so both small and large signal
are required. We'll share some of this in our DesignCon comedy session
"Bloopers and Lessons Learned".
You cannot get impedance information from a Bode plot, but you can transform
in the other direction from impedance to stability. This is discussed in our
session Killing the Bode Plot and there are many articles on the subject
including this one we published
http://powerelectronics.com/power-electronics-systems/when-bode-plots-fail-us
You cannot use the open loop gain from the manufacturer to derive a VRM model
for many reasons. This is a central focus in several of our DesignCon
presentations. In fact further, much of the published data is incorrect. We
resolve this easily by deriving our model from 3 measurements. Our
non-invasive stability assessment includes all loops, open loop and closed
loop dependent. PI Bootcamp Session 1 also shows how to get from the
impedance sweep to what we need to do to "fix it". We do not need to know
much about the controller in order to fix it and if designed properly the
design is easily tuned. The criticality is more in the capacitor selection
and we show that also as well as why we need to measure them ourselves. Some
companies do publish S-parameters for their bulk capacitors, but they
measured them using an S11 measurement. Since the ESR is two orders of
magnitude below the recommended minimum S11 impedance measurement, the
results are bogus. This capacito
r selection is where much of the attention needs to be paid and this was
the topic of a Lunch and Learn collaboration with Wurth last year. Their
aluminum polymer capacitors tend to work well for flat impedance
applications. This too is covered in the Power Integrity Bootcamp at
DesignCon.
We do have examples where we did transform from open loop plots to impedance,
but that only works for well behaved single loop systems and only below the
crossover frequency, which isn’t helpul. As regulator bandwidths increase so
does the challenge. We presented our eGaN linear regulator last year and we
are presently at a bandwidth of 500MHz in that regulator and hope to soon
reach 1GHz. There is no way to measure open loop at these frequencies as the
interconnects are too inductive. We can easily measure this using our
non-invasive stability measurement, which also works for those pesky ADC
buffer amplifiers and voltage references that tend to have very poor
stability.
The epitome of issues is apparent in the DDR termination regulators. We'll
show some of that in our DesignCon presentations also next week
-----Original Message-----
From: FreeLists Mailing List Manager [mailto:ecartis@xxxxxxxxxxxxx]
Sent: Wednesday, January 13, 2016 10:17 AM
To: si-list digest users <ecartis@xxxxxxxxxxxxx>
Subject: si-list Digest V16 #24
si-list Digest Wed, 13 Jan 2016 Volume: 16 Issue: 024
In This Issue:
#1: From: "Istvan Nagy" <buenoshun@xxxxxxxxx>
Subject: [SI-LIST] VRM bode plot transformation into output imp
profi
#2: From: istvan.novak@xxxxxxxxxxx
Subject: [SI-LIST] Re: VRM bode plot transformation into output
imp p
#3: From: Faraydon Pakbaz <pakbazf@xxxxxxxxxx>
Subject: [SI-LIST] Re: VRM bode plot transformation into output
imp p
#4: From: Don Pakbaz <don.pakbaz@xxxxxxxxxxxxxxxxxxx>
Subject: [SI-LIST] Fwd: VRM bode plot transformation into
output imp
#5: From: Charles Hymowitz <charles@xxxxxxxx>
Subject: [SI-LIST] Re: VRM bode plot transformation into output
imp
#6: From: "He, Jiangqi" <jiangqi.he@xxxxxxxxx>
Subject: [SI-LIST] Re: VRM bode plot transformation into output
imp
#7: From: <Steve@xxxxxxxxxxxx>
Subject: [SI-LIST] Re: VRM bode plot transformation into output
imp p
#8: From: "Istvan Nagy" <buenoshun@xxxxxxxxx>
Subject: [SI-LIST] Re: VRM bode plot transformation into output
imp p
----------------------------------------------------------------------
Msg: #1 in digest
From: "Istvan Nagy" <buenoshun@xxxxxxxxx>
Subject: [SI-LIST] VRM bode plot transformation into output imp profile
Date: Wed, 13 Jan 2016 00:30:53 -0800
Hi,
This post is about theories on VRM modelling.
For power integrity analysis ideally we should combine the
frequency-responses of the VRM (output impedance profile), all the
capacitors, the power planes and maybe some properties of the chips (pin
inductance, package decaps..). I would do this combined simulation in AC
small signal mode in SPICE or ADS or similar. The model of the capacitors is
easily simulated (3-element ESL/ESR/C), the power planes can be extracted
with 2.5D-3D EM simulators into touchstone files. But, the VRM model is what
I find more problems with. Older publications suggested 2-element or
4-element lumped models that are probably not accurate at all, especially
for modern digital controllers. Building an "averaged model" would not be
possible for me, as I am not working at the VRM-chip companies. I tried to
make estimated models for VRM, but they are probably very inaccurate, as I
cannot model all the effects in the VRM with my simple spice models:
http://www.buenos.extra.hu/download/QUCS_PowerIntegrity-doc.pdf
So, I thought we could get more accurate VRM models for power delivery
system impedance profile simulation by transforming the bode plot into an
impedance profile. I think they basically describe the same thing but in
different ways, closed vs open loop and current vs voltage source being
used. Then impedance/frequency (Z-parameter) plots can be transformed into
S-parameter/frequency plots (touchstone file) in easy and known ways. Then
these touchstone files can be placed as components in AC simulation is
QUCS-spice or Agilent-ADS.
All VRM chip vendors provide simulation tools to generate "OPEN loop GAIN
(bode plot)". So we can get this plot for every project easily. Maybe we
could transform this plot into a "CLOSED loop output IMPEDANCE profile".
Most/any chip vendors don't provide tools to generate the impedance profile,
I don't know enough about the internals of each VRM to build accurate models
that I can simulate directly for output impedance, but Bode tools are common
and easily available.
The problem is, I have no idea how to transform one into the other, and no
idea whether it is possible at all. That's my missing link.
"OPEN loop GAIN (bode plot)" ==[??]==> "CLOSED loop output IMPEDANCE
profile".
What I am looking for is a reusable model, equations or tools, so for every
rail in every project I could simulate the PI quickly.
Any comments?
Is it possible?
Regards,
Istvan Nagy
Board/hardware design engineer
---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus
------------------------------
Msg: #2 in digest
Date: Wed, 13 Jan 2016 07:18:34 -0600 (CST)
From: istvan.novak@xxxxxxxxxxx
Subject: [SI-LIST] Re: VRM bode plot transformation into output imp profile
Hi Istvan,
You are not alone with this challenge, but as usual= , the answer is "it
depends",
and there is no single generic= answer to this question that could fit the
very
wide spectrum of circ= uits and applications. The first thing to keep in
mind:
as Lee o= ften reminds this list, you get what you pay for.
Going from loo= p gain to closed-loop output impedance: the theory
is there. You= dont even need to pick up one of the many books on DC-DC
converter de= signs; you can apply simple calculations of an amplifier block
with a = feedback. However, you have to set the expectations right: if you
think that your simple averaged model may not capture all of the effects,=
you should not think that using the Bode plot predicted by a vendor t= ool
(which most of them are also averaged, and capture only the first-= order
effects) will give you the details you missed in your simple mod= el; it
willnot.
The biggest challenge in these days is coming f= rom all of the secondary
effects
that are very hard to model. Ma= ny years ago converters tended to be
stand-alone, well-isolated blocks= , where source and load conditions had
less influence on the performan= ce. As we tend to reduce those
input/output
barriers to achieve = cost and size reduction, you will find that many
converters
today will= show enough 'transparency' that your output impedance also
depends
on= the source impedance. Also, if you DO count on any of the
nonlinearfunctions of modern controllers, you should not expect to capture
itw= ith a
simple SPICE model. The selection of control-loop type als= o makes a big
difference: some (like current-mode control) are more fr= iendly to simple
modeling, because they tend to be less sensitive to s= econd-order effects.
Some others, like constant ON time and hysteretic= -type controllers have
a tendency to be much more sensitive to things = like layout details, which
are much harder to capture in simple models= . Sometimes the same exact
circuit, even if you literally move t= he same components, may perform
very differently dependent on the boar= d stackup and small layout details.
Some of these challenges wer= e described in past publications, for instance
http://www.electrical-integrity.com/Paper_download_files=
/DC12_11-MP2.pdf[1]
http://www.electrical-integrity.com/Paper_downl=
oad_files/DC15_11_FR1_Paper_ImpactofRegulatorSense_point.pdf[2]
(this= second paper described second-order scenarios that should be easy
to = simulate if you have the proper averaged model for the converter.
At D= esignCon 2016 you will also find multiple talks that touch on this
su=bject
and we can chat if you attend.
We all have the desire= to do pre-layout and post-layout simulations to
capture
potential pro= blems before we build our boards. In my experience though,
unles= s we can afford significant overdesign, you should always allow for
it= erations and design changes after your first build, and the changes
shouldbe based on actual validation. This of course refers to cases wh= en
the
performance details matter; but otherwise why would you want to= do
more accurate simulations before you build the board?
R= egards,
Istvan Novak
Oracle
&nb= sp; On 01/13/16, Istvan Nagy<buenoshun@xxxxxxxxx> wrote:= Hi,
This post is about theories on VRM modelling.
For power integrity analysis ideally we should combine the
fre= quency-responses of the VRM (output impedance profile), all the
capac= itors, the power planes and maybe some properties of the chips (pin
i= nductance, package decaps..). I would do this combined simulation in AC
small signal mode in SPICE or ADS or similar. The model of the capacitor= s
is
easily simulated (3-element ESL/ESR/C), the power planes can be = extracted
with 2.5D-3D EM simulators into touchstone files. But, the = VRM model is
what
I find more problems with. Older publications sugge= sted 2-element or
4-element lumped models that are probably not accur= ate at all, especially
for modern digital controllers. Building an &q= uot;averaged model" would
notbe
possible for me, as I am not wo= rking at the VRM-chip companies. I tried to
make estimated models for= VRM, but they are probably very inaccurate, as I
cannot model all th= e effects in the VRM with my simple spice models:
http://www.buenos.extra.hu/download/QUCS_PowerIntegrity= -doc.pdf[3]
So, I thought we could get more accurate VRM models for p= ower delivery
system impedance profile simulation by transforming the= bode plot into an
impedance profile. I think they basically describe= the same thing but in
different ways, closed vs open loop and curren= t vs voltage source being
used. Then impedance/frequency (Z-parameter= ) plots can be transformed into
S-parameter/frequency plots (touchsto= ne file) in easy and known ways. Then
these touchstone files can be p= laced as components in AC simulation is
QUCS-spice or Agilent-ADS.All VRM chip vendors provide simulation tools to
generate "OPEN loo= p GAIN
(bode plot)". So we can get this plot for every project e= asily. Maybe we
could transform this plot into a "CLOSED loop ou= tput IMPEDANCE profile".
Most/any chip vendors don't provide too= ls to generate the impedance
profile,
I don't know enough about the i= nternals of each VRM to build accurate
models
that I can simulate dir= ectly for output impedance, but Bode tools are
common
and easily avai= lable.
The problem is, I have no idea how to transform one into the ot= her, and no
idea whether it is possible at all. That's my missing lin= k.
"OPEN loop GAIN (bode plot)" =3D=3D[??]=3D=3D> "C= LOSED loop output
IMPEDANCE
profile".
What I am looki= ng for is a reusable model, equations or tools, so for
every
rail in = every project I could simulate the PI quickly.
Any comments?
Is i= t possible?
Regards,
Istvan Nagy
Board/hardware design= engineer
---
This email has been checked for viruses= by Avast antivirus software.
https://www.avast.com/antivirus
------------------------------------------------------------= ------
To unsubscribe from si-list:
si-list-request= @freelists.org[5] with 'unsubscribe' in the Subject field
or to= administer your membership from a web page, go to:
h= ttp://www.freelists.org/webpage/si-list[6]
For help:
si-list-request@xxxxxxxxxxxxx[7] with 'help' in the Subject field=
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list[8]
List = archives are viewable at:
=09=09http://www.free= lists.org/archives/si-list[9]
Old (prior to June 6, 2001) list= archives are viewable at:
=09=09http://www.qsl.net/wb6tpu[10]
--- Links ---
1 3D"http://www.electrical-integrity.com/Paper_download_file=
2 3D"http:/=
3 3D"http://www.buenos.extra.hu/download/QUCS_PowerIntegrity-doc.pdf=
4 3D"https://=
5
6 3D"//www.freelists.org/webpage/si-list";
7 3D"mailto:si-list-request@xxxxxxxxxxxxx";
8 3D"http://tech.groups.yahoo.com/group/si-list";
9 3D"h=
10 3D"http=
------------------------------
Msg: #3 in digest
Subject: [SI-LIST] Re: VRM bode plot transformation into output imp profile
From: Faraydon Pakbaz <pakbazf@xxxxxxxxxx>
Date: Wed, 13 Jan 2016 08:25:10 -0500
Hi Istvan;
Interesting discussion! When you say "Open loop Gain (Bode plot)", do you
mean a plot that is generated using
1A current source and measured voltage at the output node which give
impedance as Z = V/1A ?!
If so, then one can approximate the transfer function of this open loop as
a pole residue and then from that formulate
open loop zero-pole transfer function. Once the open loop transfer function
is know it is fairly easy to come up with unity
gain closed loop transfer function. Once the closed loop transfer function
is configured( Zero-Pole), then it can get
converted to passive model (R, L and C) and/or S-parameters. I have done
this for PLLs with knowledge of only closed
loop plot. I am a Matlab Guy :-) so I do all of these using Matlab RF
tool box and Simpower specifically but once the
Passive model(R, L and C) and or S-Parameter is know then it is easy to
take it to any other tools that understand passive
model and/or S-parameter. I am hoping that I am understanding your
question correctly. Let me know....
Regards;
Don Pakbaz
From: "Istvan Nagy" <buenoshun@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: 01/13/2016 03:32 AM
Subject: [SI-LIST] VRM bode plot transformation into output imp profile
Sent by: si-list-bounce@xxxxxxxxxxxxx
Hi,
This post is about theories on VRM modelling.
For power integrity analysis ideally we should combine the
frequency-responses of the VRM (output impedance profile), all the
capacitors, the power planes and maybe some properties of the chips (pin
inductance, package decaps..). I would do this combined simulation in AC
small signal mode in SPICE or ADS or similar. The model of the capacitors
is
easily simulated (3-element ESL/ESR/C), the power planes can be extracted
with 2.5D-3D EM simulators into touchstone files. But, the VRM model is
what
I find more problems with. Older publications suggested 2-element or
4-element lumped models that are probably not accurate at all, especially
for modern digital controllers. Building an "averaged model" would not be
possible for me, as I am not working at the VRM-chip companies. I tried to
make estimated models for VRM, but they are probably very inaccurate, as I
cannot model all the effects in the VRM with my simple spice models:
http://www.buenos.extra.hu/download/QUCS_PowerIntegrity-doc.pdf
So, I thought we could get more accurate VRM models for power delivery
system impedance profile simulation by transforming the bode plot into an
impedance profile. I think they basically describe the same thing but in
different ways, closed vs open loop and current vs voltage source being
used. Then impedance/frequency (Z-parameter) plots can be transformed into
S-parameter/frequency plots (touchstone file) in easy and known ways. Then
these touchstone files can be placed as components in AC simulation is
QUCS-spice or Agilent-ADS.
All VRM chip vendors provide simulation tools to generate "OPEN loop GAIN
(bode plot)". So we can get this plot for every project easily. Maybe we
could transform this plot into a "CLOSED loop output IMPEDANCE profile".
Most/any chip vendors don't provide tools to generate the impedance
profile,
I don't know enough about the internals of each VRM to build accurate
models
that I can simulate directly for output impedance, but Bode tools are
common
and easily available.
The problem is, I have no idea how to transform one into the other, and no
idea whether it is possible at all. That's my missing link.
"OPEN loop GAIN (bode plot)" ==[??]==> "CLOSED loop output IMPEDANCE
profile".
What I am looking for is a reusable model, equations or tools, so for every
rail in every project I could simulate the PI quickly.
Any comments?
Is it possible?
Regards,
Istvan Nagy
Board/hardware design engineer
---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------
Msg: #4 in digest
Date: Wed, 13 Jan 2016 08:59:46 -0500
Subject: [SI-LIST] Fwd: VRM bode plot transformation into output imp
From: Don Pakbaz <don.pakbaz@xxxxxxxxxxxxxxxxxxx>
---------- Forwarded message ----------
From: Don Pakbaz <don.pakbaz@xxxxxxxxxxxxxxxxxxx>
Date: Wed, Jan 13, 2016 at 8:43 AM
Subject: VRM bode plot transformation into output imp
To: Istvan Nagy <buenoshun@xxxxxxxxx>
Cc: si-list@xxxxxxxxxxxxx
Hi Istvan;
Interesting discussion! When you say "Open loop Gain (Bode plot)", do you
mean a plot that is generated using
1A current source and measured voltage at the output node which give
impedance as Z = V/1A ?!
If so, then one can approximate the transfer function of this open loop as
a pole residue and then from that formulate
open loop zero-pole transfer function. Once the open loop transfer function
is know it is fairly easy to come up with unity
gain closed loop transfer function. Once the closed loop transfer function
is configured( Zero-Pole), then it can get
converted to passive model (R, L and C) and/or S-parameters. I have done
this for PLLs with knowledge of only closed
loop plot. I am a Matlab Guy :-) so I do all of these using Matlab RF
tool box and Simpower specifically but once the
Passive model(R, L and C) and or S-Parameter is know then it is easy to
take it to any other tools that understand passive
model and/or S-parameter. I am hoping that I am understanding your
question correctly. Let me know....
Regards;
Don Pakbaz
From: "Istvan Nagy" <buenoshun@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: 01/13/2016 03:32 AM
Subject: [SI-LIST] VRM bode plot transformation into output
imp
profile
Sent by: si-list-bounce@xxxxxxxxxxxxx
Hi,
This post is about theories on VRM modelling.
For power integrity analysis ideally we should combine the
frequency-responses of the VRM (output impedance profile), all the
capacitors, the power planes and maybe some properties of the chips (pin
inductance, package decaps..). I would do this combined simulation in AC
small signal mode in SPICE or ADS or similar. The model of the capacitors
is
easily simulated (3-element ESL/ESR/C), the power planes can be extracted
with 2.5D-3D EM simulators into touchstone files. But, the VRM model is
what
I find more problems with. Older publications suggested 2-element or
4-element lumped models that are probably not accurate at all, especially
for modern digital controllers. Building an "averaged model" would not be
possible for me, as I am not working at the VRM-chip companies. I tried to
make estimated models for VRM, but they are probably very inaccurate, as I
cannot model all the effects in the VRM with my simple spice models:
http://www.buenos.extra.hu/download/QUCS_PowerIntegrity-doc.pdf
So, I thought we could get more accurate VRM models for power delivery
system impedance profile simulation by transforming the bode plot into an
impedance profile. I think they basically describe the same thing but in
different ways, closed vs open loop and current vs voltage source being
used. Then impedance/frequency (Z-parameter) plots can be transformed into
S-parameter/frequency plots (touchstone file) in easy and known ways. Then
these touchstone files can be placed as components in AC simulation is
QUCS-spice or Agilent-ADS.
All VRM chip vendors provide simulation tools to generate "OPEN loop GAIN
(bode plot)". So we can get this plot for every project easily. Maybe we
could transform this plot into a "CLOSED loop output IMPEDANCE profile".
Most/any chip vendors don't provide tools to generate the impedance
profile,
I don't know enough about the internals of each VRM to build accurate
models
that I can simulate directly for output impedance, but Bode tools are
common
and easily available.
The problem is, I have no idea how to transform one into the other, and no
idea whether it is possible at all. That's my missing link.
"OPEN loop GAIN (bode plot)" ==[??]==> "CLOSED loop output IMPEDANCE
profile".
What I am looking for is a reusable model, equations or tools, so for every
rail in every project I could simulate the PI quickly.
Any comments?
Is it possible?
Regards,
Istvan Nagy
Board/hardware design engineer
---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
