[SI-LIST] si with ibis model
- From: "lauwell009" <lauwell009@xxxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 22 Oct 2009 20:05:42 +0800
Content-Type: text/plain;
charset="gb2312"
Content-Transfer-Encoding: 7bit
Hello,
when I use IBIS model for si analysis,comparing IBIS model to I\O HSPICE
model of altera's Stratix_II_GX FPGA,I find that the output signal of IBIS
delays more at fall edge than at rise.In the picture,white line is the input
signal,blue line is the output signal of IBIS model and red line is the output
signal of Hspice model.The load conditions are both same in simulations.
what happened in my simulation?can anybody tell me the reason ?
2009-10-22
Best regards
wei.liu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
