[SI-LIST] Re: setup & hold Time for source synchronous

  • From: "Lai, Ricky (Eng Hou)" <Ricky.Lai@xxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Tue, 7 Aug 2001 11:38:06 -0500

I agree with your analysis and your equation can generally apply to almost
all source-synchronous design.  However, on most of the source-synchronous
systems that I have seen, the drivers and receivers are well balanced, i.e. 
T_available_setup_time_at_driver = T_available_hold_time_at_driver
and
Tsetup_at_receiver = Thold_at_receiver.
In such cases, the board designers will route the board where the data and
clock (or strobe) with identical trace length.  As a result, the
Tflight_skew_max will be identical in both equations.

Ricky


-----Original Message-----
From: Bill Chen [mailto:billchen@xxxxxxxxxxx]
Sent: Monday, August 06, 2001 8:01 PM
To: Issa, Elie; Lai, Ricky (Eng Hou); si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: setup & hold Time for source synchronous




   I don't agree with Richy's  Equations.
In the equation given, Tflight_skew_max is subtracted
in both setup and hold equations and this is incorrect.
If the Tfligh_skew reduces your setup margin, it may
increase your hold time margin. On the other hand, if it
improves you setup margin, it will reduce your hold time
margin. That's the reason that design engineers sometimes
on purposely skew the data / clock signals to balance
setup / hold time margins.

   Here is my version of setup/hold equations for your
reference:

Tsetup_margin = T_available_setup_time_at_driver   -
        T_interconnect_flight_skew_clk_leading_data_max -
        Tsetup_at_receiver

Thold_margin = T_available_hold_time_at_driver   -
        T_interconnect_flight_skew_clk_trailing_data_max -
        Thold_at_receiver

  Where:  T_available_setup_time_at_driver and
          T_available_hold_time_at_driver
          are Time data_valid_before_clock_min and
              Time data_valid_after_clock_min

         and
          T_interconnect_flight_skew_clk_leading_data_max,
          T_interconnect_flight_skew_clk_trailing_data_max
         are skew between data and clock signals with reference
         to clock signal. please  note that these two terms may
         be positive or negative. So the skew may increase or
         decrease setup or hold time margin.

         For example, if clock is actually skew more than data
         signals, the T_interconnect_flight_skew_clk_leading_data_max
         becomes a negative number, the maximum time clock leading
         data should use the minimum absolute skew between clock and
         data {Think about Max(-1ns, -1.2ns, -1.5ns) = -1ns}.
         And in this  situation, the setup margin is improved
         comparing with 0 skew between clk/data. Same principal
         holds true for the other term.



  Let me know if you have any comments!

Thanks!

======================================================
Bill (Qinghua) Chen, Ph.D.

Technical Leader
Andiamo Systems Inc.
375 E. Tasman Dr. Bldg 6    Phone: (408)527-4982
San Jose, CA 95134          Email: billchen@xxxxxxxxxxx
======================================================





  Let me know if you have any questions.

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Issa, Elie
Sent: Friday, August 03, 2001 2:49 PM
To: Lai, Ricky (Eng Hou); 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: setup & hold Time for source synchronous



Thanks!

-----Original Message-----
From: Lai, Ricky (Eng Hou)
Sent: Friday, August 03, 2001 1:44 PM
To: Issa, Elie; 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: setup & hold Time for source synchronous



The correct equation should be:
Setup margin = Budget - (T_data_valid_before_stb_min) - (Tflight_skew_max) -
Tsetup
Hold margin  = Budget - (T_data_valid_after_stb_min) - (Tflight_skew_max) -
Thold

-----Original Message-----
From: Issa, Elie
Sent: Friday, August 03, 2001 11:26 AM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] setup & hold Time for source synchronous



Dear SI Gurus:
I need  your help in verifying some derivation for setup & hold equations
for GTL bus
for source synchronous clocks.

The equation for setup is:
Tco(strobe)min + Tflight(strobe)min - Tco(data)max -Tflight(data)max
-Tsetup= Tmargin_setup

The equation for hold time was:
Tco(data)min    + Tflight(data)min  -Tco(strobe)max -Tflight(strobe)max
-Thold= Tmargin_hold

The skew for the strobe & data  flight time should be very small.  Whenever,
I fit the variable given in the
specs into the equation, the margin comes negative.

I would think that there must be a ValidBefore and ValidAfter variable to be
included in the equation.
Yet the specs claim the ValidBefore is only [Tco(strobe)min-- Tco(data)max].


Any input would be greatly appreciated!

Regards
Elie



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