[SI-LIST] Re: routing of DDR clock signals
- From: "Henrik Gild" <hencox@xxxxxxxxxxx>
- To: weirsp@xxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Mon, 16 Aug 2004 14:58:08 +0200
Hi!
>Henrik, if you are new at this, you will probably get the best results by
>treating the pair as a loosely coupled differential pair. That means
>providing greater than normal horizontal spacing between the CK and CK#
>than normal signals. Then the differential impedance will be close to 2X
>the normal mode impedance of each line.
Should the differential impedance of the CK+CK# pair actually be 100ohm or
50ohm? To reach for example 50ohm differential impedance, should I set the
individual width of CK and CK# so they equal 25ohm normal mode impedance?
If I use 6 mil signals, what distance between the CK and the CK# signals
would you recommend?
I'm connecting this SO-DIMM to a Spartan3 FPGA. Do I need to switch to
another signal standard on the pins of the FPGA acting as the CK and CK#
signals (like LVDS) because they are differential on the board, or will
normal SSTL2 suite well anyway?
Many questions... :)
>Additionally, timing aberrations caused by crosstalk can be reduced by
>affording 5H spacing between either CK or CK# and the nearest outside
>neighbor signal.
Do you include other DDR signals as well in the "neighbor signal" group?
I'm not sure what you mean by 5H, is it five times the normal distance
between tracks?
> Remember that you are matching electrical length. The easiest way to do
>that is to keep the physical routes reasonably close together and then
>match physical length.
Thanks a lot for your answers!
/Henrik
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