[SI-LIST] routing of DDR clock signals
- From: "Henrik Gild" <hencox@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 16 Aug 2004 13:38:34 +0200
Hi!
This is my first post to this list. Looking at some previous posts I'm sure
you'll be able to answer this one for me:
When routing DDR SDRAM signals (ordinary DDR1, 166MHz, DDR333), should the
CK and CK# lines be treated as a differential pair or just like any other
signals (like DQ or DQS) only that they should be of equal length? I had a
look in the datasheet on the MT46V16M16 from Micron and it didn't say
anything about differential clock lines, just that the signal edges has to
coincide time-wise. But the clock signals were described as differential in
their IBIS model...
Thanks
/Henrik Gildå, B.S.CE
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