[SI-LIST] Re: resitor packs vs networks in DDR design
- From: Stefan Ludwig <ludwig@xxxxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 29 Jul 2004 09:14:46 +0200
Hi Alex,
I assume you're talking about end termination for the DQ and A/C lines,
not Vref, which is the reference voltage for the VREF pins.
Do not use resistor networks for Vtt. They will have one or maybe two
connections to Vtt. The resulting high mounting inductance will cause
the "terminated" lines to influence each other. If you have 50 Ohm from
the terminated line to 1 shared Vtt pin, it also means you have 100 Ohm
between each terminated line. The result will be that if all lines
except one are driven with 0 and the remaining line with 1, it can be
pulled to a value below Vih of the IO spec. It is sort of the same
effect as ground bounce.
We once had to debug a customer design where they used resistor packs
but had long shared traces from the resistor pack to vias to the Vtt
plane. The same effect as described above happened and the DDR memory
system was not working.
I would advise against resistor networks in general except for
pullsomewheres in the kOhm range.
Regards,
Stefan Ludwig
Alex Jose wrote:
>Hi,
>
>I am curious about knowing the impact of using resistor networks instead
>of resistor packs for the 50E pull ups to Vref on the DDR bus?
>All the design guides I checked seem to use resistor packs. Any idea
>whether using resistor networks instead of resistor packs will have any
>impact on signal integrity?
>
> Thanks and Regards,
>Alex Jose,
>
>
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