[SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance
- From: Vinu Arumugham <vinu@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 30 Jul 2012 10:03:40 -0700
"I assumed no ISI since most jitter tolerance compliance only requires
sinusoidal jitter"
All the specifications I am aware of (XAUI, XFI,SFI, XLAUI,CEI) require
sinusoidal jitter to be applied in addition to all other sources of
jitter for jitter tolerance tests.
A jitter tolerance test with sinusoidal jitter alone is a rarely a good
stress test.
Thanks,
Vinu
On 07/29/2012 10:51 AM, Jory McKinley wrote:
> Hello Chris/Mark,
> I assumed no ISI since most jitter tolerance compliance only requires
> sinusoidal jitter and IF the the output of the RX CDR is used to re-time the
> TX then the first order roll-off of the jitter transfer will be very close to
> the unity level roll-off of the jitter tolerance curve, I have seen this in
> about a handful of different serdes lab measurements. As Mark mentioned
> there is a relationship that can be drawn in the roll-off region of jitter
> transfer and under 1UI for jitter tolerance which is what you are after. The
> relationships break down when the TX side of traffic is generated not from
> the CDR of the RX but internal "clean" PLL originating from an external
> crystal.
> -Jory
>
>
>
> ________________________________
> From: "Cheng, Chris" <chris.cheng@xxxxxx>
> To: mark <mark@xxxxxxxxxxxxxx>
> Cc: si-list <si-list@xxxxxxxxxxxxx>
> Sent: Saturday, July 28, 2012 3:44 PM
> Subject: [SI-LIST] Re: relationship between reeceiver jitter transfer and
> jitter tolerance
>
> Mark,
> I should clarify my original statement. The pattern is sent by a BERT
> instrument, at the receiver pin with minimal ISI. The motivation for this
> exercise is that it is almost impossible to put high speed device to loop
> back mode and observe jitter transfer. I am hoping the "jitter tolerance"
> described can be an alternative for it.
> Chris
>
> Sent from my iPad
>
> On Jul 28, 2012, at 11:00 AM, "mark" <mark@xxxxxxxxxxxxxx> wrote:
>
>> Chris,
>> When a data pattern is introduced to jitter tolerance then ISI is introduced
>> as a term. The ISI may be sufficient to close the EYE vertically and also
>> close the EYE horizontally. Receive equalization attempts to recover some of
>> the loss due to ISI. The ISI that is not compensated for has been called
>> non-compensable jitter in some circles. Lets say we have 20% UI on
>> non-compensable jitter.
>>
>> Then to your question:
>> a) if the jitter tolerance is greater than 1 UI is the jitter transfer equal
>> to 1?
>> No. for two reasons.
>> 1) jitter tolerance consists of the ISI + sinusoidal jitter. The jitter
>> tolerance at high frequency is limited by the closure due to ISI and the
>> receive CDR circuit design. Say the receive circuit needs 30% opening and
>> the ISI due to your CJTPAT is 20%. The high frequency jitter tolerance is ~
>> 50%. So sinusoidally modulated jitter up to 50% can be applied at high
>> frequencies. When the
>> 2) even with no ISI or circuit related jitter tolerance, the pure jitter
>> tolerance of an ideal CDR is +- 0.5 UI at high frequency, Then as a the CDR
>> tracks the incoming jitter the tolerance can increase. Also the dynamics 2nd
>> order or 3rd order behavior can make the jitter tolerance actually decease
>> initially before increasing.
>>
>> So in total the high frequency jitter tolerance is < 1 UI due to ISI and
>> circuit reasons, and the point at which jitter tolerance grows to 1 UI is a
>> function of the transfer function shape and the starting point at high
>> frequency. A receiver with 0.1UI high frequency tolerance will have a
>> different frequency of modulation for 1 UI tolerance for the same CDR TF as
>> a receiver with 0.8UI high frequency tolerance.
>>
>> For b)
>> Jitter tolerance is a grade of exceeding a threshold. The phase error is the
>> input jitter*(1-jitter transfer). So
>> The equation is closer to jitter tolerance = input_jitter*(1-transfer) -
>> "constant"
>>
>>
>> This is true for all frequencies and amplitudes of jitter.
>>
>> Best Regards,
>> Mark
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>> Behalf Of Cheng, Chris
>> Sent: Friday, July 27, 2012 7:08 PM
>> To: si-list
>> Subject: [SI-LIST] relationship between reeceiver jitter transfer and jitter
>> tolerance
>>
>> Hi there,
>>
>> I think the classical definition of jitter transfer is related to how much
>> jitter at the input of receiver get transfered to the output of the
>> receiver.
>> The classical definition of jitter tolerance is related to how much input
>> reference clock jitter is acceptable for a given bit error rate.
>> What if I modify slightly the definition of jitter tolerance to the receiver
>> as, how much jitter can be applied to the input (instead of reference clock)
>> before you have a receiver error.
>> A practical way of doing the above is to send a known pattern such as CJTPAT
>> to a receiver and then modulate it with a fixed frequency jitter. The
>> minimum jitter amplitude that will trigger errors will be defined as jitter
>> tolerance as above.
>> So my question is, if one does the experiment above and plot out the jitter
>> tolerance vs. frequency. How does that receiver jitter tolerance related to
>> the receiver transfer curve ?
>> Can I interpret the receiver jitter tolerance and transfer relationship as:
>> a) For jitter tolerance > UI, the jitter transfer is 1 or unity
>> b) For jitter tolerance < UI, the jitter transfer = UI - jitter tolerance -
>> "some constant"
>> where "some constant" is probably related to the setup and hold requirements
>> of the receiver
>>
>> Thanks in advanced,
>>
>> Chris Cheng
>> Distinguished Technologist , Electrical
>> Hewlett-Packard Company
>>
>> +1 510 413 5977 / Tel
>> chris.cheng@xxxxxx / Email
>> 4209 Technology Dr
>> Fremont, CA 94538
>> USA
>>
>>
>>
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