[SI-LIST] Re: regarding PCI-Express clocking scheme - dazzled & confused

  • From: Knut Georg Wiljugrein <kwiljugrein@xxxxxxxxx>
  • To: roymesi@xxxxxxxxx
  • Date: Tue, 27 Sep 2005 16:25:45 +0200

Hi Roy,

PCI-E uses serial transmission on each individual lane, and stripe 
packets across the number of lanes in a link when multiple lanes are 
available.  On each lane, 8b/10b coding is used to guarantee DC balance 
and sufficient number of transisions to allow the receiver to regenerate 
the clock from the 8b/10b encoded signal.

The transmission rate is 2.5Gb/s on each of the serial lanes. Because of 
the 8b/10b coding, sending 1 byte of data takes 10, rather than 8 bits. 
Thus, the 2.5 Gb/s (before coding) equals 250MB/s (after coding) Btw. 
also keep in mind that when talking about transmission rates giga- and 
mega- means 10^9 and 10^6, not 2^30 and 2^20 this is often confused.

So, with a x16 link, you have 16 x 250MB/s, which is 4GB/s in total, not 
per lane as you wrote (, but I figure that was a typo)

Since the clock is embedded in the data stream, the 100MHz REFCLK seems 
superficial. It is however needed when the transmitter side runs on a 
spread-spectrum clock to reduce EMI. The frequency of the transmitter 
clock then varies in frequency (relatively slowly) but over a range than 
can not be tracked by the receiver running from a fixed nominal 
reference frequency generated by a local free running oscillator. 
Instead, the receiver actually need to use the same reference clock as 
the transmitter to be in synch with the frequency deviation caused by 
the spread spectrum function, and this is the 100MHz REFCLK signal.

In many embedded systems (e.g. VXS systems), the host board is known NOT 
to use a spread spectrum clock, and the REFCLK is not needed. However 
for PC plugin cards (e.g. graphics cards) the motherboard is unknown, 
and may well use spread spectrum.

Regards,
Knut Georg W.


Roy M wrote:

>Hi all,
>I'm working on a PCI-E board for quite a while now, and I'm trying to
>figure something out here, regarding the clock scheme of the PCI-E.
>I've looked through the spec. of PCI-E and from wondering around the
>net i found a few things that don't match up:
>
>1. I understand that the transmission rate is 250 MB/S/lane, hence, if
>I have x16link, then the tx rate will be 4GB/S/lane, BUT, i've read in
>few places (including the Spec.) that the idea in PCI-E is that one
>does not transmit clock, but rather 8b10b encoded data, and from this
>the other end re-create the recieve clock. how does that settle?
>
>2. also, there's a 100MHz clock which is called a reference clock,
>that IS transmitted... how does that settle with remark 1) ?
>
>3. furthermore, what is the 2.5Gb/s tx rate, which ussually, when
>people talk about PCI-E, they through it in the air...? 2.5Gb/s is not
>250MB/s/lane...
>
>if anyone will be able to explain all that to me ,it will be great,
>cause i'm all messed up around here...
>Thanks guys and girls!
>Roy
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