[SI-LIST] ragu-doubt on pull up resistance plz help
- From: ragu amar <raguamar@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 24 Nov 2004 08:26:28 -0800 (PST)
Hi all,
Iam beginner in board design. Iam having one doubt in pull up resistance. If
i give pull up in any cmos gate or ttl gate input, what it will take the
whether it is 0 or 1 or...
1. what is pull up?
2. Can i drive pull up for any cmos or ttl device for logic 1. is it correct?
3. In i2c protocol SCL and SDA both are open drain? if not why SCL is pull up?
4. what is intermediate voltage range for cmos devices and ttl devices?
plz answer anybody
best regards,
raguraman
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