Hi Gert,
It looks to me that the old Railway Specification made sense back then,
given the state of PCB industry at that time. This was the time when
what is known today as the ZBC (Zycon Buried Capacitance) 2-mil
glass-reinforced laminate with RTF foil became available in the
industry. People figured out a way to avoid shorts that was the result
from rough copper and/or voids left in the fabricated boards due to
contamination in the manufacturing process. Smooth copper in various
forms are available today, as well as laminates without glass
reinforcement, both of which are helpful in avoiding potential shorts.
Hipot testing can help to weed out direct shorts, but voids potentially
left due to contamination is harder to detect and shorts created by CAF
(https://en.wikipedia.org/wiki/Conductive_anodic_filament) may appear
over time. For products where long-term reliability is very important,
these concerns and risk factors have to be taken seriously. This having
said, over the past 25 years the PCB industry made a lot of progress and
what was risky back then, could be made safe today. Convincing a
customer, on the other hand, is a different thing. I remember that when
we introduced the 1-mil non-reinforced laminates into our large rigid
boards at SUN, it took years to go through the proper and convincing
qualification process.
I am sure that our friends from the PCB industry will add more details
and insight.
Best regards,
Istvan Novak
SUN
On 9/18/2020 8:28 AM, Havermann, Gert wrote:
This is to all the PCB Experts (sorry, it is a bit off topic):------------------------------------------------------------------
I have a customer requiring a minimum dielectric thickness between all metal
layers in a Backplane to be always thicker than 0.4mm and at the same time,
the overall thickness is restricted. There is no way to lower the layer
count, so I started questioning the 0.4mm rule. It turned out that it is
based on an old Railway Specification from 1995 where it is stated that:
“only a minimum dielectric thickness of >400µm can guarantee to avoid shorts
during pressing and to maintain the isolation resistance”
The spec doesn’t specify any minimum isolation resistance, so I can’t do any
functional proof of thinner dielectric. I did a calculation of the dielectric
strength and isolation resistance of the used material compared to “old FR-4
Minimum performance specifications” which helped in the discussion, but the
customer is still not convinced that anything below 0.4mm will prevent shorts
during pressing even though there are 3 Prepregs in between.
To give you some numbers: our stack will have 0.39mm thickness by design,
thus 0.35mm at worst case theoretical minimum tolerance on 1oc copper with
85% copper fill, so technically this is absolutely save (Max 120V on L2, 48V
between L15 and 16, all other Layers GND and Differential signaling). They
don’t even allow to just lower the dielectric thickness on the pure ethernet
signaling layers.
Long story, now the question is: Does anyone of you know of any old Study
showing the risk of shorts between layers during pressing? Or maybe some
notes about discussions of that time in IPC or anywhere? I’d really like to
find out where this rule is technically coming from to be able to convince
the customer that this rule is no longer valid.
BR
Gert
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