Hello Sam,
Welcome to the SI-LIST. Please note that attachments do not get through
on the list; you can post it somewhere and just include the link.
Not having seen what the attachment would have been and assuming that
you have radiated EMI issue due to ringing that shows up on the SVID
signal, you may want to check first the layout and routing of the SVID
signal to make sure it does not loose its reference plane(s). High
frequency noise associated with DC-DC converters, especially if the
noise appears to be load dependent, may come from second-order effects
of the circuit and layout: parasitic inductances and capacitances create
resonances that may get excited by the fast edges of the switching
waveform. Load dependency usually indicates that your inductor may
approach saturation. With an appropriate 2.5D or 3D field solver you
should be able to simulate and identify the coupling path, but
simulating the excitation source signal may get tricky, unless you get
all parasitics (layout and switching device junction capacitances and
parasitic inductances) correctly. Alternately, you can nail it down
with targeted experiments, which mechanism creates the source.
If you already have a board that you rather do not spin, and can afford
a little lower efficiency, you can try to lower the excitation magnitude
by slowing the switching waveform edges: by lowering the supply voltage
of the drive circuit, increasing the series gate resistor (if you have
that in your circuit) value driving the output FETs or changing the
snubber circuit values (if you already have one layed out). You can try
to add snubber circuit with manual rework if you dont have it on the
board already.
Regards,
Istvan Novak
Oracle
On 6/5/2015 5:32 AM, Sam Lyu wrote:
Hello everyone, I' am a new guy in the SI/PI simulation field and very
excited to have such place to ask question about what I encountered in the
real case.
I try my best to describe the situation what I encountered if anything is
unclear, please let me know.
Below is the layout and the waveform of SVID signal at 0A and 35A loading.
The blue plane is synchronous buck converter switching node which is a EMI
source as it's switching
and the yellow plane is the power rail Vcc of the SVID signal.
I guess the noise source on SVID signal is coming from the EMI noise(blue
plane), because as the loading increase, the noise is more severe.
But now I need some suggestion about how to simulate that situation to verify
my thought because the EMI could couple to the signal directly or indirectly
by influence of Vcc rail(yellow plane). Anyway the EMI coupling path is
everywhere so if anyone has some idea on how to start to deal with this
problem, please email me.
I'm very appreciate to all of you to read this mail.
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Best Regards,
Sam Lyu
SI Engineer, RDII
System Solution
Lite-On Technology Corp.
Tel: 886-2-2222-6181 Ext 3312
Fax: 886-2-2226-3559
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