Hello everyone, I' am a new guy in the SI/PI simulation field and very excited
to have such place to ask question about what I encountered in the real case.
I try my best to describe the situation what I encountered if anything is
unclear, please let me know.
Below is the layout and the waveform of SVID signal at 0A and 35A loading.
The blue plane is synchronous buck converter switching node which is a EMI
source as it's switching
and the yellow plane is the power rail Vcc of the SVID signal.
I guess the noise source on SVID signal is coming from the EMI noise(blue
plane), because as the loading increase, the noise is more severe.
But now I need some suggestion about how to simulate that situation to verify
my thought because the EMI could couple to the signal directly or indirectly by
influence of Vcc rail(yellow plane). Anyway the EMI coupling path is everywhere
so if anyone has some idea on how to start to deal with this problem, please
email me.
I'm very appreciate to all of you to read this mail.
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Best Regards,
Sam Lyu
SI Engineer, RDII
System Solution
Lite-On Technology Corp.
Tel: 886-2-2222-6181 Ext 3312
Fax: 886-2-2226-3559
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