[SI-LIST] Re: pwr-gnd loop inductance measurment
- From: Ray Anderson <Raymond.Anderson@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 23 Oct 2002 13:06:55 -0700 (PDT)
>
>
>Ray and friends,
>
>I am always curious in the days of flip chip BGA's how does one view the
>pwr/gnd loop inductance of a package ?
>Does the core pwr/gnd current really flow through the BGA pwr/gnd planes or
>does it really flow straight up from the C4 bump under the die through the
>via from the PCB ?
Depends on the exact package configuration, but a number
of designs do indeed have current flowing through the
package planes.
>Does the presence of power/gnd planes in a BGA is more to
>do with referencing the I/O and for the switching current to return. In the
>later case measuring the pwr/gnd loop inductance is meaningless unless the
>on die decoupling is presence and a specific I/O loop is known.
As you know, on-die decoupling is pretty common these
days, especially for core power in high-performance
processors.
I/O power inductance is a whole separate issue compared
to core power inductance.
>
>In other words, why do we even need to measure the pwr/gnd plane loop
>inductance ?
Could be for a lot of reasons. One obvious one is to determine
one of the elements in an accurate package resonance model.
>
>Chris
-Ray
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