[SI-LIST] (probably naive) FPGA PDS questions
- From: "Glenn Judd" <glennj+@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Sun, 27 Jun 2004 01:02:12 -0400
Without desiring to rehash the "Decoupling capacitors"
thread from 2002 (a very helpful thread), I have a=20
few PDS/decap questions:
Question 1
I'm designing a PDS for an FPGA right now, but I'm=20
unsure of my target Z since I'm unsure what
transient current my FPGA (XC2V250FG256) is capable=20
of drawing. Xilinx's XAPP623 doc mentions using
measurements to determine this, but doesn't mention
how to do this before fab.=20
What they do mention is to use the number of pins=20
as a rough guide on the number of caps. Using that
guide, I've come up with the following:=20
http://gs229.sp.cs.cmu.edu/vcc1.5.jpeg. I'm concerned,
however, that that may not be good enough, but
getting lower would require more caps which would
seem to fly in the face of the 1-cap-per-pin rule
(the design shown is already using somewhat=20
more than 1-cap-per-pin).
Question 2
My analysis also seems to indicate that life might be
better _without_ planar capacitance as shown on
this plot (red is without planar capacitance):=20
http://gs229.sp.cs.cmu.edu/vcc1.5withoutPlanarCap.jpeg
(I plan on running the FPGA @ 200MHz.)
Is that right? This is counterintuitive. I'm guessing
that since real anti-resonance spikes (i.e.
not using my tool's "generic" model) aren't nearly
so bad, this plot might be misleading.
Question 3
I've frequently seen designs that use only 47uf, 4.7uf,
and 0.1uf capacitors. I've also seen many people
advocate using only 1 high speed decap size to
mitigate anti-resonance issues. My experiments=20
with my homebrew impedance analysis tool (see below)=20
seem to indicate that without using several values
of caps, Z will be quite high over a broad range
of frequencies. In addition to several high
frequency cap values, low Z in the lower frequencies
required a low-ESR bulk capacitor > 200uf.
How are those designs working?
I understand that fewer values =3D fewer anti-resonance=20
peaks, but I can't see how a decently low Z can be met
over a broad range of frequencies with this approach
(without _huge_ numbers of capacitors).
(I'm guessing that this is a point of controversy,
so replying directly to me on this point is probably
best since I don't want to re-ignite something
that's probably dealt with somewhere in the archives
that I couldn't find.)
Thanks.
Glenn
p.s. The plots above were generated with a simple tool=20
that I've tossed together for doing the obvious Z
calculation, but using some real cap data.
The tool is current up at:
http://gs229.sp.cs.cmu.edu/PDSAnalyzer.html.
It requires JDK1.4+ or JavaPlugin etc. (It won't be up =20
permanently.)
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