[SI-LIST] Re: prescalar

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: bolisudha@xxxxxxxxx
  • Date: Mon, 08 Oct 2007 23:01:50 -0700

If it's exactly repeating /9 /7 /9 /7 it sounds like a logic design 
error.  If it's random /9 /7 then it sounds like timing problems.  Phase 
switch designs have very strict timing relationships that must be 
maintained to operate reliably.  I am not a big fan of the vicious 
timing.  I would look at the timing of a /9 /8 LFSR.  I think you will 
find that even though the whole circuit has to work at the full clock 
rate, the timing margins are better than the phase switch method.

Steve.
boli sudha wrote:
> hi iam designing synthesizer for WLAN applications at 5 GHz so iam designing
> 8/9 prescalar for that.i have designed using phase switch architecture.i got
> /8 output .but when contrl is 1 iam not geting divide by 9.for that iam
> getting divided by 9 and 7 alternatively.so please help me
> Thanks & Regards
> Sudhakar
>
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