[SI-LIST] Re: ppm related question
- From: "Anand Srinivasan" <sanand@xxxxxxxxxxxx>
- To: "steve weir" <weirsi@xxxxxxxxxx>
- Date: Tue, 15 Apr 2008 21:57:24 -0700
Thanks Steve,
As you said that ethernet is designed to use independent clocks. The
problem that I am seeing is due to the fact that I am transmitting at
100% line rate all the time for testing purpose and am seeing the fifo's
overrunning. (though in real systems ethernet will be a bursty traffic).
I have a strange observation that in none of previous switches did I
have to reduce the ppm in IXIA to trasmit data at 100% line rate, but I
am required to do so in this switch. I believe that in any set-up there
be a clock variation between the sending and receiving parties. At 100%
line rates shouldn't this accumulation lead to overruns or underruns on
the buffers or fifo's all the time?
Thanks,
Anand
=20
-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]=20
Sent: Wednesday, April 16, 2008 10:15 AM
To: Anand Srinivasan
Cc: Si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] ppm related question
Anand,
1. Yes, a PLL generates a slave clock that tracks the reference within=20
the bandwidth of the loop, subject to disturbances affecting the VCO.
2. No, variation means any deviation from the reference up to and=20
including the specified limit. Usually this is unsigned as for example:
+/-50ppm
3. Yes, there are many SI and PI phenomena that impair clock timing.
4. Yes, PLL, DLL etc.
Ethernet is designed to use independent rather than hierarchical clocks.
You should not need to lock clocks between stations.
Steve.
Anand Srinivasan wrote:
> Hi All,
> I have an IXIA packet generator/analyzer providing ethernet data
streams
> to my switch. I am finding that the switch is receiving data at a rate
> that is slightly higher than the rate at which switch is transmitting
> data. I attribute this to some clock ppm variations in the switch. I
> have some questions related to the ppm variation in clocks:
> =20
> 1. If i have a clock of X MHz and if i feed this clock to a pll to
get
> a clock of freq Y Mhz, will the ppm variation of the clocks X and Y
> remain the same?
> 2. When we state that there is a +100 ppm variation from X MHz in the
> clock, does this mean that the clock now is a constant frequency of (X
> MHz + 100ppm)? or does it dynamically vary between X MHz and (X MHz +
> 100ppm)?
> 3. Would signal integrities issues on the board affect ppm variations
in
> clocks?
> 4. Is there any on-board correction methodologies that can be applied
to
> adjust the ppm variations in clocks?
> =20
> Thanks,
> Anand
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