[SI-LIST] Re: ppm related question
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Anand Srinivasan <sanand@xxxxxxxxxxxx>
- Date: Tue, 15 Apr 2008 21:44:33 -0700
Anand,
1. Yes, a PLL generates a slave clock that tracks the reference within
the bandwidth of the loop, subject to disturbances affecting the VCO.
2. No, variation means any deviation from the reference up to and
including the specified limit. Usually this is unsigned as for example:
+/-50ppm
3. Yes, there are many SI and PI phenomena that impair clock timing.
4. Yes, PLL, DLL etc.
Ethernet is designed to use independent rather than hierarchical clocks.
You should not need to lock clocks between stations.
Steve.
Anand Srinivasan wrote:
> Hi All,
> I have an IXIA packet generator/analyzer providing ethernet data streams
> to my switch. I am finding that the switch is receiving data at a rate
> that is slightly higher than the rate at which switch is transmitting
> data. I attribute this to some clock ppm variations in the switch. I
> have some questions related to the ppm variation in clocks:
>
> 1. If i have a clock of X MHz and if i feed this clock to a pll to get
> a clock of freq Y Mhz, will the ppm variation of the clocks X and Y
> remain the same?
> 2. When we state that there is a +100 ppm variation from X MHz in the
> clock, does this mean that the clock now is a constant frequency of (X
> MHz + 100ppm)? or does it dynamically vary between X MHz and (X MHz +
> 100ppm)?
> 3. Would signal integrities issues on the board affect ppm variations in
> clocks?
> 4. Is there any on-board correction methodologies that can be applied to
> adjust the ppm variations in clocks?
>
> Thanks,
> Anand
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