[SI-LIST] Re: power planes (4-layer-board)
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Daniel Bauer <daniel.bauer16@xxxxxx>
- Date: Mon, 16 Feb 2009 16:53:59 -0800
Daniel, there are only two cases where you would be concerned with this:
1. The PCB power system has to directly support the I/O switching
current. The reality of package inductance is such that as rise times
get short, the PCB can't directly support the I/O, charge store to
support the I/O long enough for current to overcome the inductance and
distribution time delay has to be located in the package and/or on the
die. Ideally you can find out from your IC manufacturers what their
packages look like. In practice you often can't. If you have IC's that
are a big concern, our metrology lab in Oregon can characterize them for
you. The Oregon contact number is at the bottom of my signature.
2. Signals switch return references between power rails injecting I/O
current directly into the power cavity. Your layout proposal wisely
seeks to avoid this by maintaining Vss as the return reference.
Steve
Daniel Bauer wrote:
> Hi,
>
> do you know any rule of thumb for the maximal size of such an power island
> versus the signal frequency / signal rise (fall) time? Only a default
> example: power island with one dimension in x direction of 12cm has a
> bare-board resonance of approximately 244MHz; which max rise time / signal
> frequency should the signal have?
>
>
> David, could you please tell me the reasons for the restrictions for the
> stripline calculation (http://emclab.mst.edu/pcbtlc2/stripline.html)?
> W/(H-T) < 0.35; T/H <0.25;
>
> best regards
> Daniel
>
>
>
>
>> Daniel, as you propose this will work very well. It avoids injecting
>> return current into a high impedance power cavity which can become an
>> EMI / SI / PI nightmare. Just be sure to stitch the GND shapes on layer
>> 3 well to layer 2 and manage the impedances and isolation as needed of
>> your power islands.
>>
>> Steve.
>> Daniel Bauer wrote:
>>
>>> Hi,
>>>
>>> the standard layout for an 4-layer PCB is, using outer layers for the
>>> signals and the two inner layers for one ground and one power plane. The
>>> power plane seems to have a few advantages as well as disadvantages (using
>>> an 4-layer board).
>>>
>>> If a trace running at the top layer has to change to the bottom layer -
>>> also the return current has to change the layer (using stitched
>>> capacitors).
>>>
>>> What do you think about the proposal to use the third layer for ground as
>>> well as for power? On every position where an signal trace is running at
>>> the bottom layer, the third layer will be a ground plane, connected to the
>>> ground plane on the second layer.... and when there`s no trace on the
>>> bottom layer I will use an power plane on the third layer. From this it
>>> follows that I will get some power islands on the third layer which were
>>> connected with traces on the bottom or top layer. The complete return
>>> current should use the ground plane (which has an lower impedance) and not
>>> one of the small power islands.
>>>
>>> Would there be an impedance change for the signal traces changing the layer
>>> (top to bottom or vica versa) when both inner layers will use an ground
>>> plane where the signal is running?
>>>
>>>
>>> x----------| (top layer - signal layer)
>>> GND | GND (second layer is a complete ground plane)
>>> Power | GND (ground and power islands)
>>> |---------x (bottom layer - signal layer)
>>>
>>> The line will show a signal trace changing from the top to the bottom
>>> layer. Both ground planes using at the inner layers, will be connected
>>> together by many vias. Could you tell me if this would be a good decision
>>> improving signal integrity? Are there any kind of disadvantages?
>>>
>>>
>>> best regards
>>> Daniel
>>>
>>>
>>>
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>> --
>> Steve Weir
>> Teraspeed Consulting Group LLC
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--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
California office
(866) 675-4630 Business
(707) 780-1951 Fax
Main office
(401) 284-1827 Business
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http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of
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