[SI-LIST] Re: power on RAMP
- From: "Jon Keeble" <jkeeble@xxxxxxxxxxxx>
- To: <aowens@xxxxxxxxxxxxxxxxxx>
- Date: Thu, 5 Dec 2002 09:59:40 +1100
The shape and timescale of power coming on, on each rail in a system, can be
responsible for parts failing to initialise properly.
Controlling hardware reset may not help. I've had problems with both FPGAs
and ASICs.
Some early versions of (recently released) FPGAs required ramp times of
under 100 usec.
This was admittedly a bug. that was rectified in a later version of the
part.
However, the bug would have prevented delivery of systems (with serious
commercial consequences).
Fortunately, the system has centralised JTAG support (the parts could be
got going by issuing an 'INITIALISE' command via JTAG).
Power supplies often include specific circuits to slow down the ramp: rapid
ramps stress both the supply and the load.
I've had experience where the supply manufacturer has assisted in changing
values to get adequate ramps.
The problem can be compounded by having different parts on the same rail
with conflicting ramp reqiurements.
A solution is to provide power switches between components and supplies as
required.
These are the same parts used for hot-plug; adding hot pluggability may be
useful for system test or even to the end user.
Another solution is to run backplanes at one voltage (say 12, 24, or 48v)
and provide DCDC convertors on all cards.
The system supply may be cheaper, as only one rail is required.
This also simplifies current sharing supplies used in redundant systems, and
simplifies battery backup.
Use of DCDC convertors is in any case increasing to meet the demands of ever
decreasing Vcore supply rails.
>
> Nico Fleurinck wrote:
>
> > Dear all,
> > For a virtex-II FPGA (XC2V2000) the power-on ramp must be minimum 1ms
and
> > maximum 50ms.
> > Can anybody tell me how you can control the power on ramp of a certain
> > voltage.
> > Please let me know how you can do it.
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