[SI-LIST] plane inductance

From: Ivor Bowden <bowden.ivor@xxxxxxxxx>
To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Date: Tue, 14 Oct 2014 01:20:57 -0700
Hi SI experts,
Please consider this case:
Two adjacent planes.
One is used as high power ground plane.
The other as low power ground plane.
The two planes are tied together at just one spot.

What are the concerns about current transients on the high 
power plane inducing voltage differentials on the low power 
plane via mutual inductance?

Of course this scenario is full of "depends", e.g.
How close are the planes?
What is the dielectric between them?
How big are the currents?
Where are they going?
Where are the power return planes?
etc.

I could construct a simulation and dial in these factors and 
see.

But before doing that, I was hoping for some wisdom from 
those that have experience with such things. For example, is 
this seldom an issue at all or is it a more common problem? 
Any examples / studies?

To add more context, we can use some hypothetical detail.
For example:
PCB is a typical small board - about the size of a CD case.
Stackup is typical 0.063 12 layer with 1/2 oz copper and 
usual glass / resin pre-preg, layers separated by a few mils.
Typical density of reliefs dotting the planes, but no slots.
Power connector on one edge, power device on other edge, so 
currents flow across the board.
Current transients around 1A/nS with peaks of a few amps on 
power ground plane.
Power nets loosely coupled with power ground plane, a few 
layers away.
Low power plane AC currents are insignificantly small.
On low power plane we don't want more than a few mV between 
any pair of points.

Another consideration is where to connect the two planes, e.g
At the power input point (assuming just one)?
At a corner?
Considering low current density along the edges, at all 4 
corners?
In the middle?

Your comments are welcome.

Thank you,
Ivor Bowden


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[SI-LIST] plane inductance

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